^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * interrupt controller support for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_INT_RISC_MASK0 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_INT_RISC_MASK1 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_INT_RISC_LEVEL0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIRFSOC_INT_RISC_LEVEL1 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIRFSOC_INIT_IRQ_ID 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_INT_BASE_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIRFSOC_NUM_IRQS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct irq_domain *sirfsoc_irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __iomem *sirfsoc_irq_get_regbase(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return (void __iomem __force *)sirfsoc_irqdomain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static __init void sirfsoc_alloc_gc(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int set = IRQ_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) handle_level_irq, clr, set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *base = sirfsoc_irq_get_regbase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int __init sirfsoc_irq_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) panic("unable to map intc cpu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &irq_generic_chip_ops, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sirfsoc_alloc_gc(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) set_handle_irq(sirfsoc_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sirfsoc_irq_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 level0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 level1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct sirfsoc_irq_status sirfsoc_irq_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int sirfsoc_irq_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *base = sirfsoc_irq_get_regbase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void sirfsoc_irq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *base = sirfsoc_irq_get_regbase();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct syscore_ops sirfsoc_irq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .suspend = sirfsoc_irq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .resume = sirfsoc_irq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int __init sirfsoc_irq_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!sirfsoc_irqdomain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) register_syscore_ops(&sirfsoc_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) device_initcall(sirfsoc_irq_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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