^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 Regents of the University of California
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017-2018 SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Western Digital Corporation or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) "riscv-intc: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct irq_domain *intc_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (unlikely(cause >= BITS_PER_LONG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) panic("unexpected interrupt cause");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) switch (cause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) case RV_IRQ_SOFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * We only use software interrupts to pass IPIs, so if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * non-SMP system gets one, then we don't know what to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) handle_IPI(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) handle_domain_irq(intc_domain, cause, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * On RISC-V systems local interrupts are masked or unmasked by writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * on the local hart, these functions can only be called on the hart that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * corresponds to the IRQ chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void riscv_intc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) csr_clear(CSR_IE, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void riscv_intc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) csr_set(CSR_IE, BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int riscv_intc_cpu_starting(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) csr_set(CSR_IE, BIT(RV_IRQ_SOFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int riscv_intc_cpu_dying(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) csr_clear(CSR_IE, BIT(RV_IRQ_SOFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct irq_chip riscv_intc_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "RISC-V INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .irq_mask = riscv_intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .irq_unmask = riscv_intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) handle_percpu_devid_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct irq_domain_ops riscv_intc_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .map = riscv_intc_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int __init riscv_intc_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int rc, hartid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) hartid = riscv_of_parent_hartid(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (hartid < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pr_warn("unable to find hart id for %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * The DT will have one INTC DT node under each CPU (or HART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * DT node so riscv_intc_init() function will be called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * for each INTC DT node. We only need to do INTC initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * for the INTC DT node belonging to boot CPU (or boot HART).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &riscv_intc_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!intc_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("unable to add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rc = set_handle_irq(&riscv_intc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_err("failed to set irq handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "irqchip/riscv/intc:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) riscv_intc_cpu_starting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) riscv_intc_cpu_dying);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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