^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas IRQC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* SYS-CPU vs. RT-CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* IRQn Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct irqc_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int requested_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct irqc_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct irqc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *cpu_int_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct irqc_irq irq[IRQC_IRQ_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int number_of_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) atomic_t wakeup_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct irqc_priv *irq_data_to_priv(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void irqc_dbg(struct irqc_irq *i, char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_dbg(i->p->dev, "%s (%d:%d)\n", str, i->requested_irq, i->hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [IRQ_TYPE_LEVEL_LOW] = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [IRQ_TYPE_LEVEL_HIGH] = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct irqc_priv *p = irq_data_to_priv(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irqc_dbg(&p->irq[hw_irq], "sense");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tmp &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tmp |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct irqc_priv *p = irq_data_to_priv(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) atomic_inc(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) atomic_dec(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct irqc_irq *i = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct irqc_priv *p = i->p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 bit = BIT(i->hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) irqc_dbg(i, "demux1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ioread32(p->iomem + DETECT_STATUS) & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) iowrite32(bit, p->iomem + DETECT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) irqc_dbg(i, "demux2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int irqc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct irqc_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct resource *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) p->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (k = 0; k < IRQC_IRQ_MAX; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) p->irq[k].p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) p->irq[k].hw_irq = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) p->irq[k].requested_irq = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) p->number_of_irqs = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (p->number_of_irqs < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(dev, "not enough IRQ resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto err_runtime_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* ioremap IOMEM and setup read/write callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) p->iomem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(p->iomem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = PTR_ERR(p->iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto err_runtime_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) p->irq_domain = irq_domain_add_linear(dev->of_node, p->number_of_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &irq_generic_chip_ops, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!p->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(dev, "cannot initialize irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err_runtime_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 1, "irqc", handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0, 0, IRQ_GC_INIT_NESTED_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(dev, "cannot allocate generic chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto err_remove_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) p->gc->reg_base = p->cpu_int_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) p->gc->chip_types[0].regs.enable = IRQC_EN_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) p->gc->chip_types[0].regs.disable = IRQC_EN_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) p->gc->chip_types[0].chip.parent_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* request interrupts one by one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (k = 0; k < p->number_of_irqs; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (devm_request_irq(dev, p->irq[k].requested_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irqc_irq_handler, 0, name, &p->irq[k])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dev, "failed to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto err_remove_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) err_remove_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) irq_domain_remove(p->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) err_runtime_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int irqc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct irqc_priv *p = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) irq_domain_remove(p->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int __maybe_unused irqc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct irqc_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (atomic_read(&p->wakeup_path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) device_set_wakeup_path(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct of_device_id irqc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .compatible = "renesas,irqc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DEVICE_TABLE(of, irqc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct platform_driver irqc_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .probe = irqc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .remove = irqc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "renesas_irqc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .of_match_table = irqc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .pm = &irqc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int __init irqc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return platform_driver_register(&irqc_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) postcore_initcall(irqc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __exit irqc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) platform_driver_unregister(&irqc_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_exit(irqc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DESCRIPTION("Renesas IRQC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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