^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas INTC External IRQ Pin Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INTC_IRQPIN_REG_NR_MANDATORY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTC_IRQPIN_REG_NR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* INTC external IRQ PIN hardware register access:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * PRIO is read-write 32-bit with 4-bits per IRQ (**)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * (*) May be accessed by more than one driver instance - lock needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * (**) Read-modify-write access by one driver instance - lock needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * (***) Accessed by one driver instance only - no locking needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct intc_irqpin_iomem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long (*read)(void __iomem *iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void (*write)(void __iomem *iomem, unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct intc_irqpin_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int requested_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int domain_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct intc_irqpin_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct intc_irqpin_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int sense_bitfield_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) atomic_t wakeup_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned shared_irqs:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 shared_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct intc_irqpin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int irlm_bit; /* -1 if non-existent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static unsigned long intc_irqpin_read32(void __iomem *iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ioread32(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static unsigned long intc_irqpin_read8(void __iomem *iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ioread8(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iowrite32(data, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite8(data, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct intc_irqpin_iomem *i = &p->iomem[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return i->read(i->iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int reg, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct intc_irqpin_iomem *i = &p->iomem[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) i->write(i->iomem, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int reg, int hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return BIT((p->iomem[reg].width - 1) - hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int reg, int hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int reg, int shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int width, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tmp = intc_irqpin_read(p, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tmp &= ~(((1 << width) - 1) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tmp |= value << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) intc_irqpin_write(p, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int irq, int do_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int bitfield_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int shift = 32 - (irq + 1) * bitfield_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) shift, bitfield_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) do_mask ? 0 : (1 << bitfield_width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* The SENSE register is assumed to be 32-bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int bitfield_width = p->sense_bitfield_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int shift = 32 - (irq + 1) * bitfield_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (value >= (1 << bitfield_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bitfield_width, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) str, i->requested_irq, i->hw_irq, i->domain_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void intc_irqpin_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) intc_irqpin_dbg(&p->irq[hw_irq], "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void intc_irqpin_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) intc_irqpin_dbg(&p->irq[hw_irq], "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void intc_irqpin_shared_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) p->shared_irq_mask &= ~BIT(hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void intc_irqpin_shared_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) p->shared_irq_mask |= BIT(hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void intc_irqpin_irq_enable_force(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) intc_irqpin_irq_enable(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* enable interrupt through parent interrupt controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * assumes non-shared interrupt with 1:1 mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * needed for busted IRQs on some SoCs like sh73a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void intc_irqpin_irq_disable_force(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* disable interrupt through parent interrupt controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * assumes non-shared interrupt with 1:1 mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * needed for busted IRQs on some SoCs like sh73a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) intc_irqpin_irq_disable(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define INTC_IRQ_SENSE_VALID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!(value & INTC_IRQ_SENSE_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) value ^ INTC_IRQ_SENSE_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int hw_irq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) atomic_inc(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) atomic_dec(&p->wakeup_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct intc_irqpin_irq *i = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct intc_irqpin_priv *p = i->p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) intc_irqpin_dbg(i, "demux1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) intc_irqpin_dbg(i, "demux2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) generic_handle_irq(i->domain_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct intc_irqpin_priv *p = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) irqreturn_t status = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (k = 0; k < 8; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (reg_source & BIT(7 - k)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (BIT(k) & p->shared_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * different category than their parents, so it won't report false recursion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct lock_class_key intc_irqpin_irq_lock_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* And this is for the request mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct lock_class_key intc_irqpin_irq_request_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct intc_irqpin_priv *p = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) p->irq[hw].domain_irq = virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) p->irq[hw].hw_irq = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) intc_irqpin_dbg(&p->irq[hw], "map");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) irq_set_chip_data(virq, h->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &intc_irqpin_irq_request_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .map = intc_irqpin_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .irlm_bit = 23, /* ICR0.IRLM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct intc_irqpin_config intc_irqpin_rmobile = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .irlm_bit = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct of_device_id intc_irqpin_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .compatible = "renesas,intc-irqpin", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .compatible = "renesas,intc-irqpin-r8a7778",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .data = &intc_irqpin_irlm_r8a777x },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .compatible = "renesas,intc-irqpin-r8a7779",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .data = &intc_irqpin_irlm_r8a777x },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .compatible = "renesas,intc-irqpin-r8a7740",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .data = &intc_irqpin_rmobile },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .compatible = "renesas,intc-irqpin-sh73a0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .data = &intc_irqpin_rmobile },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int intc_irqpin_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const struct intc_irqpin_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct intc_irqpin_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct intc_irqpin_iomem *i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct resource *io[INTC_IRQPIN_REG_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct resource *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void (*enable_fn)(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void (*disable_fn)(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bool control_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int ref_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* deal with driver instance configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) of_property_read_u32(dev->of_node, "sense-bitfield-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) &p->sense_bitfield_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) control_parent = of_property_read_bool(dev->of_node, "control-parent");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!p->sense_bitfield_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) p->sense_bitfield_width = 4; /* default to 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) p->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) config = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* get hold of register banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) memset(io, 0, sizeof(io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(dev, "not enough IOMEM resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (k = 0; k < INTC_IRQPIN_MAX; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) p->irq[k].p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) p->irq[k].requested_irq = irq->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) nirqs = k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (nirqs < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(dev, "not enough IRQ resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* ioremap IOMEM and setup read/write callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) i = &p->iomem[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* handle optional registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!io[k])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) switch (resource_size(io[k])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) i->width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) i->read = intc_irqpin_read8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i->write = intc_irqpin_write8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) i->width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) i->read = intc_irqpin_read32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) i->write = intc_irqpin_write32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev, "IOMEM size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i->iomem = devm_ioremap(dev, io[k]->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) resource_size(io[k]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!i->iomem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(dev, "failed to remap IOMEM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* configure "individual IRQ mode" where needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (config && config->irlm_bit >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (io[INTC_IRQPIN_REG_IRLM])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) config->irlm_bit, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_warn(dev, "unable to select IRLM mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* mask all interrupts using priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (k = 0; k < nirqs; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) intc_irqpin_mask_unmask_prio(p, k, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* scan for shared interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ref_irq = p->irq[0].requested_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) p->shared_irqs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (k = 1; k < nirqs; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ref_irq != p->irq[k].requested_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) p->shared_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* use more severe masking method if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (control_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) enable_fn = intc_irqpin_irq_enable_force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) disable_fn = intc_irqpin_irq_disable_force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else if (!p->shared_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enable_fn = intc_irqpin_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) disable_fn = intc_irqpin_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) enable_fn = intc_irqpin_shared_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) disable_fn = intc_irqpin_shared_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) irq_chip = &p->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) irq_chip->name = "intc-irqpin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) irq_chip->parent_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) irq_chip->irq_mask = disable_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) irq_chip->irq_unmask = enable_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) irq_chip->irq_set_type = intc_irqpin_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &intc_irqpin_irq_domain_ops, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!p->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(dev, "cannot initialize irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (p->shared_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* request one shared interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (devm_request_irq(dev, p->irq[0].requested_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) intc_irqpin_shared_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) IRQF_SHARED, name, p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(dev, "failed to request low IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* request interrupts one by one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (k = 0; k < nirqs; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (devm_request_irq(dev, p->irq[k].requested_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) intc_irqpin_irq_handler, 0, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) &p->irq[k])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(dev, "failed to request low IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* unmask all interrupts on prio level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) for (k = 0; k < nirqs; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) intc_irqpin_mask_unmask_prio(p, k, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_info(dev, "driving %d irqs\n", nirqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) irq_domain_remove(p->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int intc_irqpin_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) irq_domain_remove(p->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int __maybe_unused intc_irqpin_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct intc_irqpin_priv *p = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (atomic_read(&p->wakeup_path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) device_set_wakeup_path(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct platform_driver intc_irqpin_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .probe = intc_irqpin_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .remove = intc_irqpin_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "renesas_intc_irqpin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .of_match_table = intc_irqpin_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .pm = &intc_irqpin_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int __init intc_irqpin_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return platform_driver_register(&intc_irqpin_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) postcore_initcall(intc_irqpin_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void __exit intc_irqpin_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) platform_driver_unregister(&intc_irqpin_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) module_exit(intc_irqpin_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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