^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * H8S interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static void *intc_baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IPRA (intc_baseaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const unsigned char ipr_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void h8s_disable_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned short pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int irq = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pos = (ipr_table[irq - 16] & 0x0f) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pri = ~(0x000f << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pri &= readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writew(pri, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void h8s_enable_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned short pri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int irq = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pos = (ipr_table[irq - 16] & 0x0f) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pri = ~(0x000f << pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pri &= readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pri |= 1 << pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writew(pri, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct irq_chip h8s_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "H8S-INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .irq_enable = h8s_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .irq_disable = h8s_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static __init int irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) irq_hw_number_t hw_irq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct irq_domain_ops irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .map = irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int __init h8s_intc_of_init(struct device_node *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) intc_baseaddr = of_iomap(intc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BUG_ON(!intc_baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* All interrupt priority is 0 (disable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* IPRA to IPRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (n = 0; n <= 'k' - 'a'; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writew(0x0000, IPRA + (n * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) BUG_ON(!domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq_set_default_host(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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