Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * H8/300H interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const char ipr_bit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 7,  6,  5,  5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 4,  4,  4,  4,  3,  3,  3,  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 2,  2,  2,  2,  1,  1,  1,  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	 0,  0,  0,  0, 15, 15, 15, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	14, 14, 14, 14, 13, 13, 13, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	-1, -1, -1, -1, 11, 11, 11, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	10, 10, 10, 10,  9,  9,  9,  9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void __iomem *intc_baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPR (intc_baseaddr + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void h8300h_disable_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	int irq = data->irq - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	bit = ipr_bit[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (bit >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		if (bit < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			ctrl_bclr(bit & 7, IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			ctrl_bclr(bit & 7, (IPR+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void h8300h_enable_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	int irq = data->irq - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bit = ipr_bit[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	if (bit >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		if (bit < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			ctrl_bset(bit & 7, IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			ctrl_bset(bit & 7, (IPR+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct irq_chip h8300h_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.name		= "H8/300H-INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.irq_enable	= h8300h_enable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	.irq_disable	= h8300h_disable_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		   irq_hw_number_t hw_irq_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)        irq_set_chip_and_handler(virq, &h8300h_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)        return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct irq_domain_ops irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)        .map    = irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)        .xlate  = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int __init h8300h_intc_of_init(struct device_node *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 				      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	intc_baseaddr = of_iomap(intc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	BUG_ON(!intc_baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	/* All interrupt priority low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	writeb(0x00, IPR + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	writeb(0x00, IPR + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	BUG_ON(!domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	irq_set_default_host(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IRQCHIP_DECLARE(h8300h_intc, "renesas,h8300h-intc", h8300h_intc_of_init);