^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PRU-ICSS INTC IRQChip driver for various TI SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author(s):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Andrew F. Davis <afd@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Suman Anna <s-anna@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2019 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Number of host interrupts reaching the main MPU sub-system. Note that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * is not the same as the total number of host interrupts supported by the PRUSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * INTC instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX_NUM_HOST_IRQS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* minimum starting host interrupt number for MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FIRST_PRU_HOST_INT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PRU_ICSS_INTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRU_INTC_REVID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PRU_INTC_CR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PRU_INTC_GER 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PRU_INTC_GNLR 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PRU_INTC_SISR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PRU_INTC_SICR 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PRU_INTC_EISR 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PRU_INTC_EICR 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PRU_INTC_HIEISR 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PRU_INTC_HIDISR 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PRU_INTC_GPIR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PRU_INTC_SRSR(x) (0x0200 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PRU_INTC_SECR(x) (0x0280 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PRU_INTC_ESR(x) (0x0300 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PRU_INTC_ECR(x) (0x0380 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PRU_INTC_CMR(x) (0x0400 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PRU_INTC_HMR(x) (0x0800 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PRU_INTC_SITR(x) (0x0d80 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PRU_INTC_HIER 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* CMR register bit-field macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMR_EVT_MAP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMR_EVT_MAP_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMR_EVT_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* HMR register bit-field macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HMR_CH_MAP_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HMR_CH_MAP_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HMR_CH_PER_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* HIPIR register bit-fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define INTC_HIPIR_NONE_HINT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAX_PRU_SYS_EVENTS 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX_PRU_CHANNELS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * struct pruss_intc_map_record - keeps track of actual mapping state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @value: The currently mapped value (channel or host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @ref_count: Keeps track of number of current users of this resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pruss_intc_map_record {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct pruss_intc_match_data - match data to handle SoC variations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @num_system_events: number of input system events handled by the PRUSS INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @num_host_events: number of host events (which is equal to number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * channels) supported by the PRUSS INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pruss_intc_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 num_system_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 num_host_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct pruss_intc - PRUSS interrupt controller structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @event_channel: current state of system event to channel mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @channel_host: current state of channel to host mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @base: base virtual address of INTC register space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @domain: irq domain for this interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @soc_config: cached PRUSS INTC IP configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @dev: PRUSS INTC device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @lock: mutex to serialize interrupts mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pruss_intc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int irqs[MAX_NUM_HOST_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct pruss_intc_match_data *soc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mutex lock; /* PRUSS INTC lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * struct pruss_host_irq_data - PRUSS host irq data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @intc: PRUSS interrupt controller pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @host_irq: host irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pruss_host_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pruss_intc *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 host_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return readl_relaxed(intc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void pruss_intc_write_reg(struct pruss_intc *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel_relaxed(val, intc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 idx, offset, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) idx = evt / CMR_EVT_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) offset = (evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val &= ~(CMR_EVT_MAP_MASK << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val |= ch << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void pruss_intc_update_hmr(struct pruss_intc *intc, u8 ch, u8 host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 idx, offset, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) idx = ch / HMR_CH_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) offset = (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val &= ~(HMR_CH_MAP_MASK << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val |= host << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_dbg(intc->dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * pruss_intc_map() - configure the PRUSS INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @intc: PRUSS interrupt controller pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @hwirq: the system event number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Configures the PRUSS INTC with the provided configuration from the one parsed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * in the xlate function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct device *dev = intc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 ch, host, reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mutex_lock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) intc->event_channel[hwirq].ref_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ch = intc->event_channel[hwirq].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) host = intc->channel_host[ch].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pruss_intc_update_cmr(intc, hwirq, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg_idx = hwirq / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = BIT(hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* clear and enable system event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (++intc->channel_host[ch].ref_count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pruss_intc_update_hmr(intc, ch, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* enable host interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_dbg(dev, "mapped system_event = %lu channel = %d host = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hwirq, ch, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mutex_unlock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * pruss_intc_unmap() - unconfigure the PRUSS INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @intc: PRUSS interrupt controller pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @hwirq: the system event number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Undo whatever was done in pruss_intc_map() for a PRU core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Mappings are reference counted, so resources are only disabled when there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * are no longer any users.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 ch, host, reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_lock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ch = intc->event_channel[hwirq].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) host = intc->channel_host[ch].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (--intc->channel_host[ch].ref_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* disable host interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* clear the map using reset value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pruss_intc_update_hmr(intc, ch, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) intc->event_channel[hwirq].ref_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg_idx = hwirq / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val = BIT(hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* disable system events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* clear any pending status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* clear the map using reset value 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pruss_intc_update_cmr(intc, hwirq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_dbg(intc->dev, "unmapped system_event = %lu channel = %d host = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) hwirq, ch, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mutex_unlock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void pruss_intc_init(struct pruss_intc *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) const struct pruss_intc_match_data *soc_config = intc->soc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int num_chnl_map_regs, num_host_intr_regs, num_event_type_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) num_chnl_map_regs = DIV_ROUND_UP(soc_config->num_system_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CMR_EVT_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) num_host_intr_regs = DIV_ROUND_UP(soc_config->num_host_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) HMR_CH_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) num_event_type_regs = DIV_ROUND_UP(soc_config->num_system_events, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * configure polarity (SIPR register) to active high and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * type (SITR register) to level interrupt for all system events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for (i = 0; i < num_event_type_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* clear all interrupt channel map registers, 4 events per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) for (i = 0; i < num_chnl_map_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* clear all host interrupt map registers, 4 channels per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < num_host_intr_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* global interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void pruss_intc_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void pruss_intc_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void pruss_intc_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int pruss_intc_irq_reqres(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!try_module_get(THIS_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void pruss_intc_irq_relres(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) module_put(THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enum irqchip_irq_state which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) bool *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 reg, mask, srsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (which != IRQCHIP_STATE_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) reg = PRU_INTC_SRSR(data->hwirq / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mask = BIT(data->hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) srsr = pruss_intc_read_reg(intc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *state = !!(srsr & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) enum irqchip_irq_state which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (which != IRQCHIP_STATE_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct irq_chip pruss_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .name = "pruss-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .irq_ack = pruss_intc_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .irq_mask = pruss_intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .irq_unmask = pruss_intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .irq_request_resources = pruss_intc_irq_reqres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .irq_release_resources = pruss_intc_irq_relres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .irq_get_irqchip_state = pruss_intc_irq_get_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .irq_set_irqchip_state = pruss_intc_irq_set_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int channel, int host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct device *dev = intc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_lock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* check if sysevent already assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (intc->event_channel[event].ref_count > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) intc->event_channel[event].value != channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(dev, "event %d (req. ch %d) already assigned to channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) event, channel, intc->event_channel[event].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* check if channel already assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (intc->channel_host[channel].ref_count > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) intc->channel_host[channel].value != host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) channel, host, intc->channel_host[channel].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) intc->event_channel[event].value = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) intc->channel_host[channel].value = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mutex_unlock(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned long *out_hwirq, unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct pruss_intc *intc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device *dev = intc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int ret, sys_event, channel, host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (intsize < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) sys_event = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (sys_event < 0 || sys_event >= intc->soc_config->num_system_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(dev, "%d is not valid event number\n", sys_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) channel = intspec[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (channel < 0 || channel >= intc->soc_config->num_host_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(dev, "%d is not valid channel number", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) host = intspec[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (host < 0 || host >= intc->soc_config->num_host_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(dev, "%d is not valid host irq number\n", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* check if requested sys_event was already mapped, if so validate it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = pruss_intc_validate_mapping(intc, sys_event, channel, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *out_hwirq = sys_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *out_type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct pruss_intc *intc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pruss_intc_map(intc, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) irq_set_chip_data(virq, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) irq_set_chip_and_handler(virq, &pruss_irqchip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct pruss_intc *intc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irq_set_chip_and_handler(virq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) irq_set_chip_data(virq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pruss_intc_unmap(intc, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .xlate = pruss_intc_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .map = pruss_intc_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .unmap = pruss_intc_irq_domain_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void pruss_intc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct pruss_host_irq_data *host_irq_data = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pruss_intc *intc = host_irq_data->intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 host_irq = host_irq_data->host_irq + FIRST_PRU_HOST_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 hipir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* get highest priority pending PRUSS system event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(host_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (hipir & INTC_HIPIR_NONE_HINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) hwirq = hipir & GENMASK(9, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) virq = irq_find_mapping(intc->domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * NOTE: manually ACK any system events that do not have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * handler mapped yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (WARN_ON_ONCE(!virq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const char * const irq_names[MAX_NUM_HOST_IRQS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "host_intr0", "host_intr1", "host_intr2", "host_intr3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "host_intr4", "host_intr5", "host_intr6", "host_intr7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int pruss_intc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) const struct pruss_intc_match_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct pruss_intc *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct pruss_host_irq_data *host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int i, irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 max_system_events, irqs_reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) max_system_events = data->num_system_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) intc->soc_config = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) intc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) platform_set_drvdata(pdev, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) intc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(intc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return PTR_ERR(intc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &irqs_reserved);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * The irqs-reserved is used only for some SoC's therefore not having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * this property is still valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0 && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pruss_intc_init(intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_init(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) &pruss_intc_irq_domain_ops, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!intc->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (irqs_reserved & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) irq = platform_get_irq_byname(pdev, irq_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = (irq == 0) ? -EINVAL : irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto fail_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) intc->irqs[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!host_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) goto fail_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) host_data->intc = intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) host_data->host_irq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) irq_set_handler_data(irq, host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) irq_set_chained_handler(irq, pruss_intc_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fail_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (intc->irqs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) irq_set_chained_handler_and_data(intc->irqs[i], NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) irq_domain_remove(intc->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int pruss_intc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct pruss_intc *intc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 max_system_events = intc->soc_config->num_system_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (intc->irqs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) irq_set_chained_handler_and_data(intc->irqs[i], NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (hwirq = 0; hwirq < max_system_events; hwirq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) irq_domain_remove(intc->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct pruss_intc_match_data pruss_intc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .num_system_events = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .num_host_events = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct pruss_intc_match_data icssg_intc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .num_system_events = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .num_host_events = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct of_device_id pruss_intc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .compatible = "ti,pruss-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .data = &pruss_intc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .compatible = "ti,icssg-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .data = &icssg_intc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static struct platform_driver pruss_intc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .name = "pruss-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .of_match_table = pruss_intc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .probe = pruss_intc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .remove = pruss_intc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) module_platform_driver(pruss_intc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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