Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Cristian Birsan <cristian.birsan@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Joshua Henderson <joshua.henderson@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Microchip Technology Inc.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mach-pic32/pic32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_INTCON	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_INTSTAT	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_IFS_OFFSET	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_IEC_OFFSET	0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_IPC_OFFSET	0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_OFF_OFFSET	0x0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAJPRI_MASK	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SUBPRI_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PRIORITY_MASK	0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PIC32_INT_PRI(pri, subpri)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct evic_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 irq_types[NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 ext_irqs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static struct irq_domain *evic_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static void __iomem *evic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) asmlinkage void __weak plat_irq_dispatch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int irq, hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	irq = irq_linear_revmap(evic_irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	do_IRQ(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static struct evic_chip_data *irqd_to_priv(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return (struct evic_chip_data *)data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int pic32_set_ext_polarity(int bit, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * External interrupts can be either edge rising or edge falling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * but not both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int pic32_set_type_edge(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			       unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct evic_chip_data *priv = irqd_to_priv(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -EBADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* set polarity for external interrupts only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (priv->ext_irqs[i] == data->hwirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			ret = pic32_set_ext_polarity(i, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	irqd_set_trigger_type(data, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void pic32_bind_evic_interrupt(int irq, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void pic32_set_irq_priority(int irq, int priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 reg, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	reg = irq / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	shift = (irq % 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel(PRIORITY_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writel(priority << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IRQ_REG_MASK(_hwirq, _reg, _mask)		       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	do {						       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		_reg = _hwirq / 32;			       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		_mask = 1 << (_hwirq % 32);		       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct evic_chip_data *priv = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32 iecclr, ifsclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 reg, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = irq_map_generic_chip(d, virq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * Piggyback on xlate function to move to an alternate chip as necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * at time of mapping instead of allowing the flow handler/chip to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * changed later. This requires all interrupts to be configured through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		data = irq_domain_get_irq_data(d, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		irqd_set_trigger_type(data, priv->irq_types[hw]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		irq_setup_alt_chip(data, priv->irq_types[hw]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	IRQ_REG_MASK(hw, reg, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* mask and clear flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	writel(mask, evic_base + iecclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	writel(mask, evic_base + ifsclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* default priority is required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			   const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			   irq_hw_number_t *out_hwirq, unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct evic_chip_data *priv = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (WARN_ON(intsize < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (WARN_ON(intspec[0] >= NR_IRQS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	*out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct irq_domain_ops pic32_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.map	= pic32_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.xlate	= pic32_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct device_node *node = irq_domain_get_of_node(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct evic_chip_data *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	const __le32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	const char *pname = "microchip,external-irqs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	of_property_for_each_u32(node, pname, prop, p, hwirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (i >= ARRAY_SIZE(priv->ext_irqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			pr_warn("More than %d external irq, skip rest\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				ARRAY_SIZE(priv->ext_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		priv->ext_irqs[i] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int __init pic32_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct evic_chip_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int nchips, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	nchips = DIV_ROUND_UP(NR_IRQS, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	evic_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!evic_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 						&pic32_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 						priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (!evic_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		goto err_free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * The PIC32 EVIC has a linear list of irqs and the type of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * irq is determined by the hardware peripheral the EVIC is arbitrating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * These irq types are defined in the datasheet as "persistent" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * "non-persistent" which are mapped here to level and edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * respectively. To manage the different flow handler requirements of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * each irq type, different chip_types are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					     "evic-level", handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					     clr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		goto err_domain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	board_bind_eic_interrupt = &pic32_bind_evic_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		u32 iec = REG_IEC_OFFSET + (i * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		gc->reg_base = evic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		gc->unused = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 * Level/persistent interrupts have a special requirement that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 * the condition generating the interrupt be cleared before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		 * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		 * complete the interrupt with an ack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		gc->chip_types[0].type			= IRQ_TYPE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		gc->chip_types[0].handler		= handle_fasteoi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		gc->chip_types[0].regs.ack		= ifsclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		gc->chip_types[0].regs.mask		= iec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		gc->chip_types[0].chip.name		= "evic-level";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		gc->chip_types[0].chip.irq_eoi		= irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		gc->chip_types[0].chip.irq_mask		= irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		gc->chip_types[0].chip.irq_unmask	= irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		gc->chip_types[0].chip.flags		= IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* Edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		gc->chip_types[1].type			= IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		gc->chip_types[1].handler		= handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		gc->chip_types[1].regs.ack		= ifsclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		gc->chip_types[1].regs.mask		= iec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		gc->chip_types[1].chip.name		= "evic-edge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		gc->chip_types[1].chip.irq_ack		= irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		gc->chip_types[1].chip.irq_mask		= irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		gc->chip_types[1].chip.irq_unmask	= irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		gc->chip_types[1].chip.irq_set_type	= pic32_set_type_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		gc->chip_types[1].chip.flags		= IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		gc->private = &priv[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	irq_set_default_host(evic_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * External interrupts have software configurable edge polarity. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 * interrupts are defined in DT allowing polarity to be configured only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 * for these interrupts when requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	pic32_ext_irq_of_init(evic_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) err_domain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	irq_domain_remove(evic_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err_free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	iounmap(evic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);