^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Open Multi-Processor Interrupt Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The ompic device handles IPI communication between cores in multi-core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * OpenRISC systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * For each CPU the ompic has 2 registers. The control register for sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * and acking IPIs and the status register for receiving IPIs. The register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * layouts are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * +---------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * | 31 | 30 | 29 .. 16 | 15 .. 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ----------+---------+----------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * | IRQ ACK | IRQ GEN | DST CORE | DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * +---------+---------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * +----------+-------------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | 31 | 30 | 29 .. 16 | 15 .. 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * -----------+-------------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | Reserved | IRQ Pending | SRC CORE | DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * +----------+-------------+----------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * - The ompic generates a level interrupt to the CPU PIC when a message is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ready. Messages are delivered via the memory bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - The ompic does not have any interrupt input lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - The ompic is wired to the same irq line on each core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - Devices are wired to the same irq line on each core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * +---------+ +---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * | CPU | | CPU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * | Core 0 |<==\ (memory access) /==>| Core 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * | [ PIC ]| | | | [ PIC ]|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * +----^-^--+ | | +----^-^--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * | | v v | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * <====|=|=================================|=|==> (memory bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * | | ^ ^ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * (ipi | +------|---------+--------|-------|-+ (device irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * irq | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * core0)| +------|---------|--------|-------+ (ipi irq core1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * +----o-o-+ | +--------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * | ompic |<===/ | Device |<===/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * | IPI | +--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * +--------+*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMPIC_CPUBYTES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMPIC_CTRL(cpu) (0x0 + (cpu * OMPIC_CPUBYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMPIC_STAT(cpu) (0x4 + (cpu * OMPIC_CPUBYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMPIC_CTRL_IRQ_ACK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMPIC_CTRL_IRQ_GEN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMPIC_STAT_IRQ_PENDING (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMPIC_DATA(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_PER_CPU(unsigned long, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void __iomem *ompic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ioread32be(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite32be(data, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void ompic_raise_softirq(const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int ipi_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int dst_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int src_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for_each_cpu(dst_cpu, mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * On OpenRISC the atomic set_bit() call implies a memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * barrier. Otherwise we would need: smp_wmb(); paired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * with the read in ompic_ipi_handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OMPIC_CTRL_IRQ_GEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OMPIC_CTRL_DST(dst_cpu) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) OMPIC_DATA(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long *pending_ops = &per_cpu(ops, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) while ((ops = xchg(pending_ops, 0)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * On OpenRISC the atomic xchg() call implies a memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * barrier. Otherwise we may need an smp_rmb(); paired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * with the write in ompic_raise_softirq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long ipi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ipi_msg = __ffs(ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ops &= ~(1UL << ipi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) handle_IPI(ipi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } while (ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int __init ompic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Validate the DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ompic_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_err("ompic: duplicate ompic's are not supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (of_address_to_resource(node, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_err("ompic: reg property requires an address and size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pr_err("ompic: reg size, currently %d must be at least %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) resource_size(&res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (num_possible_cpus() * OMPIC_CPUBYTES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Setup the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ompic_base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!ompic_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_err("ompic: unable to map registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pr_err("ompic: unable to parse device irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "ompic_ipi", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto out_irq_disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) set_smp_cross_call(ompic_raise_softirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out_irq_disp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) irq_dispose_mapping(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) iounmap(ompic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ompic_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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