Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * linux/arch/arm/mach-omap2/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Interrupt handler for OMAP2 boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Paul Mundt <paul.mundt@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/irqchip/irq-omap-intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* selected INTC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define INTC_REVISION		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define INTC_SYSCONFIG		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define INTC_SYSSTATUS		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define INTC_SIR		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define INTC_CONTROL		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define INTC_PROTECTION		0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define INTC_IDLE		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define INTC_THRESHOLD		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define INTC_MIR0		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define INTC_MIR_CLEAR0		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define INTC_MIR_SET0		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define INTC_PENDING_IRQ0	0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define INTC_PENDING_IRQ1	0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define INTC_PENDING_IRQ2	0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define INTC_PENDING_IRQ3	0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define INTC_ILR0		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SPURIOUSIRQ_MASK	(0x1ffffff << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define INTCPS_NR_ILR_REGS	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define INTCPS_NR_MIR_REGS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define INTC_IDLE_FUNCIDLE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define INTC_IDLE_TURBO		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define INTC_PROTECTION_ENABLE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct omap_intc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 protection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 ilr[INTCPS_NR_ILR_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 mir[INTCPS_NR_MIR_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct omap_intc_regs intc_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void __iomem *omap_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int omap_nr_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int omap_nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void intc_writel(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	writel_relaxed(val, omap_irq_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static u32 intc_readl(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return readl_relaxed(omap_irq_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) void omap_intc_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	intc_context.sysconfig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		intc_readl(INTC_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	intc_context.protection =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		intc_readl(INTC_PROTECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	intc_context.idle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		intc_readl(INTC_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	intc_context.threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		intc_readl(INTC_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	for (i = 0; i < omap_nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		intc_context.ilr[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			intc_readl((INTC_ILR0 + 0x4 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		intc_context.mir[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			intc_readl(INTC_MIR0 + (0x20 * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void omap_intc_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	intc_writel(INTC_PROTECTION, intc_context.protection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	intc_writel(INTC_IDLE, intc_context.idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	intc_writel(INTC_THRESHOLD, intc_context.threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0; i < omap_nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		intc_writel(INTC_ILR0 + 0x4 * i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				intc_context.ilr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		intc_writel(INTC_MIR0 + 0x20 * i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			intc_context.mir[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* MIRs are saved and restore with other PRCM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void omap3_intc_prepare_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * Disable autoidle as it can stall interrupt controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	intc_writel(INTC_SYSCONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void omap3_intc_resume_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Re-enable autoidle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	intc_writel(INTC_SYSCONFIG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	intc_writel(INTC_IDLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* XXX: FIQ and additional INTC support (only MPU at the moment) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void omap_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	intc_writel(INTC_CONTROL, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void omap_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	irq_gc_mask_disable_reg(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	omap_ack_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init omap_irq_soft_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	tmp = intc_readl(INTC_REVISION) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	tmp = intc_readl(INTC_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tmp |= 1 << 1;	/* soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	intc_writel(INTC_SYSCONFIG, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		/* Wait for reset to complete */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* Enable autoidle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	intc_writel(INTC_SYSCONFIG, 1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int omap_irq_pending(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	for (i = 0; i < omap_nr_pending; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void omap3_intc_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* A pending interrupt would prevent OMAP from entering suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	omap_ack_irq(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			IRQ_LEVEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		pr_warn("Failed to allocate irq chips\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	for (i = 0; i < omap_nr_pending; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		gc = irq_get_domain_generic_chip(d, 32 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		gc->reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		ct->type = IRQ_TYPE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		ct->chip.irq_ack = omap_mask_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		ct->regs.disable = INTC_MIR_SET0 + 32 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void __init omap_alloc_gc_legacy(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		unsigned int irq_start, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ct->chip.irq_ack = omap_mask_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ct->regs.enable = INTC_MIR_CLEAR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ct->regs.disable = INTC_MIR_SET0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			IRQ_NOREQUEST | IRQ_NOPROBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __init omap_init_irq_of(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	omap_irq_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (WARN_ON(!omap_irq_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	domain = irq_domain_add_linear(node, omap_nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			&irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	omap_irq_soft_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = omap_alloc_gc_of(domain, omap_irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int j, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	omap_irq_base = ioremap(base, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (WARN_ON(!omap_irq_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		pr_warn("Couldn't allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			&irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	omap_irq_soft_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	for (j = 0; j < omap_nr_irqs; j += 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void __init omap_irq_enable_protection(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	reg = intc_readl(INTC_PROTECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	reg |= INTC_PROTECTION_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	intc_writel(INTC_PROTECTION, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int __init omap_init_irq(u32 base, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * depends is still not ready for linear IRQ domains; because of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * linear IRQ Domain until that driver is finally fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (of_device_is_compatible(node, "ti,omap2-intc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			of_device_is_compatible(node, "ti,omap3-intc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (of_address_to_resource(node, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		ret = omap_init_irq_legacy(base, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	} else if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ret = omap_init_irq_of(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = omap_init_irq_legacy(base, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		omap_irq_enable_protection();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static asmlinkage void __exception_irq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) omap_intc_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	extern unsigned long irq_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	u32 irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	irqnr = intc_readl(INTC_SIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	 * A spurious IRQ can result if interrupt that triggered the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	 * sorting is no longer active during the sorting (10 INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 * functional clock cycles after interrupt assertion). Or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * change in interrupt mask affected the result during sorting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 * time. There is no special handling required except ignoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * the SIR register value just read and retrying.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 * See section 6.2.5 of AM335x TRM Literature Number: SPRUH73K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	 * Many a times, a spurious interrupt situation has been fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	 * by adding a flush for the posted write acking the IRQ in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	 * the device driver. Typically, this is going be the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 * driver whose interrupt was handled just before the spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 * IRQ occurred. Pay attention to those device drivers if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	 * run into hitting the spurious IRQ condition below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (unlikely((irqnr & SPURIOUSIRQ_MASK) == SPURIOUSIRQ_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		pr_err_once("%s: spurious irq!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		irq_err_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		omap_ack_irq(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	irqnr &= ACTIVEIRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	handle_domain_irq(domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int __init intc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			     struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	omap_nr_pending = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	omap_nr_irqs = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (WARN_ON(!node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (of_device_is_compatible(node, "ti,dm814-intc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	    of_device_is_compatible(node, "ti,dm816-intc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	    of_device_is_compatible(node, "ti,am33xx-intc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		omap_nr_irqs = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		omap_nr_pending = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ret = omap_init_irq(-1, of_node_get(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	set_handle_irq(omap_intc_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);