^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/irq/irq-nvic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 ARM Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Support for the Nested Vectored Interrupt Controller found on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ARMv7-M CPUs (Cortex-M3/M4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/v7m.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NVIC_ISER 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NVIC_ICER 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NVIC_IPR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NVIC_MAX_BANKS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 16 irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct irq_domain *nvic_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) asmlinkage void __exception_irq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int irq = irq_linear_revmap(nvic_irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) handle_IRQ(irq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) irq_map_generic_chip(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct irq_domain_ops nvic_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .translate = irq_domain_translate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .alloc = nvic_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .free = irq_domain_free_irqs_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int __init nvic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int irqs, i, ret, numbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *nvic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) numbanks = (readl_relaxed(V7M_SCS_ICTR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) nvic_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!nvic_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pr_warn("unable to map nvic registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irqs = numbanks * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (irqs > NVIC_MAX_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) irqs = NVIC_MAX_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) nvic_irq_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!nvic_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_warn("Failed to allocate irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) iounmap(nvic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "nvic_irq", handle_fasteoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clr, 0, IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_warn("Failed to allocate irq chips\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irq_domain_remove(nvic_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) iounmap(nvic_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) for (i = 0; i < numbanks; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) gc->reg_base = nvic_base + 4 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gc->chip_types[0].regs.enable = NVIC_ISER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) gc->chip_types[0].regs.disable = NVIC_ICER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* This is a no-op as end of interrupt is signaled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * exception return sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel_relaxed(~0, gc->reg_base + NVIC_ICER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Set priority on all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) for (i = 0; i < irqs; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(0, nvic_base + NVIC_IPR + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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