^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Add Alphascale ASM9260 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "alphascale_asm9260-icoll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * this device provide 4 offsets for each register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 0x0 - plain read write mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0x4 - set mode, OR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0x8 - clr mode, XOR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0xc - togle mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SET_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLR_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HW_ICOLL_VECTOR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HW_ICOLL_LEVELACK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HW_ICOLL_CTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HW_ICOLL_STAT_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HW_ICOLL_INTERRUPT0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM_ICOLL_INTR_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ICOLL_NUM_IRQS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum icoll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ICOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ASM9260_ICOLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct icoll_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *levelack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __iomem *intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum icoll_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct icoll_priv icoll_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct irq_domain *icoll_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* calculate bit offset depending on number of intterupt per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * mask lower part of hwirq to convert it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return bit << ((d->hwirq & 3) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* calculate mem offset depending on number of intterupt per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void __iomem *icoll_intr_reg(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* offset = hwirq / intr_per_reg * 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void icoll_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * The Interrupt Collector is able to prioritize irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Currently only level 0 is used. So acking can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) icoll_priv.levelack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void icoll_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __raw_writel(BM_ICOLL_INTR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void icoll_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __raw_writel(BM_ICOLL_INTR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void asm9260_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) icoll_intr_reg(d) + CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void asm9260_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) icoll_priv.clear +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ASM9260_HW_ICOLL_CLEARn(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) icoll_intr_reg(d) + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct irq_chip mxs_icoll_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irq_ack = icoll_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .irq_mask = icoll_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .irq_unmask = icoll_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .flags = IRQCHIP_MASK_ON_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct irq_chip asm9260_icoll_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .irq_ack = icoll_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .irq_mask = asm9260_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_unmask = asm9260_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = IRQCHIP_MASK_ON_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irqnr = __raw_readl(icoll_priv.stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __raw_writel(irqnr, icoll_priv.vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) handle_domain_irq(icoll_domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (icoll_priv.type == ICOLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) chip = &mxs_icoll_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) chip = &asm9260_icoll_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) irq_set_chip_and_handler(virq, chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct irq_domain_ops icoll_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .map = icoll_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void __init icoll_add_domain(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) icoll_domain = irq_domain_add_linear(np, num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &icoll_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!icoll_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) panic("%pOF: unable to create irq domain", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void __iomem * __init icoll_init_iobase(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *icoll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) icoll_base = of_io_request_and_map(np, 0, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(icoll_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) panic("%pOF: unable to map resource", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return icoll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int __init icoll_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *icoll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) icoll_priv.type = ICOLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) icoll_base = icoll_init_iobase(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) icoll_priv.clear = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Interrupt Collector reset, which initializes the priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * for each irq to level 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) stmp_reset_block(icoll_priv.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) icoll_add_domain(np, ICOLL_NUM_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int __init asm9260_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct device_node *interrupt_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void __iomem *icoll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) icoll_priv.type = ASM9260_ICOLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) icoll_base = icoll_init_iobase(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) icoll_priv.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * ASM9260 don't provide reset bit. So, we need to set level 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < 16 * 0x10; i += 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(0, icoll_priv.intr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) icoll_add_domain(np, ASM9260_NUM_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) set_handle_irq(icoll_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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