^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define pr_fmt(fmt) "mvebu-sei: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Cause register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GICP_SECR(idx) (0x0 + ((idx) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GICP_SEMR(idx) (0x20 + ((idx) * 0x4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GICP_SET_SEI_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SEI_IRQ_COUNT_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SEI_IRQ_REG_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SEI_IRQ_COUNT (SEI_IRQ_COUNT_PER_REG * SEI_IRQ_REG_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SEI_IRQ_REG_IDX(irq_id) ((irq_id) / SEI_IRQ_COUNT_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SEI_IRQ_REG_BIT(irq_id) ((irq_id) % SEI_IRQ_COUNT_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mvebu_sei_interrupt_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct mvebu_sei_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mvebu_sei_interrupt_range ap_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mvebu_sei_interrupt_range cp_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mvebu_sei {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct irq_domain *sei_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct irq_domain *ap_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct irq_domain *cp_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct mvebu_sei_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Lock on MSI allocations/releases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mutex cp_msi_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DECLARE_BITMAP(cp_msi_bitmap, SEI_IRQ_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Lock on IRQ masking register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) raw_spinlock_t mask_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void mvebu_sei_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) sei->base + GICP_SECR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void mvebu_sei_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 1 disables the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) raw_spin_lock_irqsave(&sei->mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void mvebu_sei_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct mvebu_sei *sei = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 0 enables the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) raw_spin_lock_irqsave(&sei->mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) raw_spin_unlock_irqrestore(&sei->mask_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int mvebu_sei_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct cpumask *mask_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int mvebu_sei_set_irqchip_state(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum irqchip_irq_state which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* We can only clear the pending state by acking the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (which != IRQCHIP_STATE_PENDING || state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mvebu_sei_ack_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct irq_chip mvebu_sei_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "SEI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .irq_ack = mvebu_sei_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .irq_mask = mvebu_sei_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .irq_unmask = mvebu_sei_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .irq_set_affinity = mvebu_sei_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irq_set_irqchip_state = mvebu_sei_set_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int mvebu_sei_ap_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct irq_chip mvebu_sei_ap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "AP SEI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .irq_set_type = mvebu_sei_ap_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void mvebu_sei_cp_compose_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mvebu_sei *sei = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) msg->data = data->hwirq + sei->caps->cp_range.first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) msg->address_lo = lower_32_bits(set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) msg->address_hi = upper_32_bits(set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mvebu_sei_cp_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct irq_chip mvebu_sei_cp_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "CP SEI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .irq_set_type = mvebu_sei_cp_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .irq_compose_msi_msg = mvebu_sei_cp_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int mvebu_sei_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct mvebu_sei *sei = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Not much to do, just setup the irqdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &mvebu_sei_irq_chip, sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void mvebu_sei_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) irq_set_handler(virq + i, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) irq_domain_reset_irq_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct irq_domain_ops mvebu_sei_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .alloc = mvebu_sei_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .free = mvebu_sei_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int mvebu_sei_ap_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int mvebu_sei_ap_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mvebu_sei *sei = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mvebu_sei_ap_translate(domain, arg, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) fwspec.param[0] = hwirq + sei->caps->ap_range.first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) irq_domain_set_info(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &mvebu_sei_ap_irq_chip, sei,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) handle_level_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) irq_set_probe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct irq_domain_ops mvebu_sei_ap_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .translate = mvebu_sei_ap_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .alloc = mvebu_sei_ap_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .free = irq_domain_free_irqs_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void mvebu_sei_cp_release_irq(struct mvebu_sei *sei, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_lock(&sei->cp_msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clear_bit(hwirq, sei->cp_msi_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mutex_unlock(&sei->cp_msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int mvebu_sei_cp_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int virq, unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct mvebu_sei *sei = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* The software only supports single allocations for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (nr_irqs != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mutex_lock(&sei->cp_msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) hwirq = find_first_zero_bit(sei->cp_msi_bitmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sei->caps->cp_range.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (hwirq < sei->caps->cp_range.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) set_bit(hwirq, sei->cp_msi_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mutex_unlock(&sei->cp_msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (hwirq == sei->caps->cp_range.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) fwspec.param[0] = hwirq + sei->caps->cp_range.first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) irq_domain_set_info(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) &mvebu_sei_cp_irq_chip, sei,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) handle_edge_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mvebu_sei_cp_release_irq(sei, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void mvebu_sei_cp_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct mvebu_sei *sei = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (nr_irqs != 1 || d->hwirq >= sei->caps->cp_range.size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mvebu_sei_cp_release_irq(sei, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) irq_domain_free_irqs_parent(domain, virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct irq_domain_ops mvebu_sei_cp_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .alloc = mvebu_sei_cp_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .free = mvebu_sei_cp_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct irq_chip mvebu_sei_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .name = "SEI pMSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct msi_domain_ops mvebu_sei_msi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct msi_domain_info mvebu_sei_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .ops = &mvebu_sei_msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .chip = &mvebu_sei_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void mvebu_sei_handle_cascade_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct mvebu_sei *sei = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for (idx = 0; idx < SEI_IRQ_REG_COUNT; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long irqmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) irqmap = readl_relaxed(sei->base + GICP_SECR(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for_each_set_bit(bit, &irqmap, SEI_IRQ_COUNT_PER_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hwirq = idx * SEI_IRQ_COUNT_PER_REG + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) virq = irq_find_mapping(sei->sei_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (likely(virq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_warn(sei->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "Spurious IRQ detected (hwirq %lu)\n", hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void mvebu_sei_reset(struct mvebu_sei *sei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 reg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Clear IRQ cause registers, mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int mvebu_sei_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct irq_domain *plat_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mvebu_sei *sei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!sei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sei->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mutex_init(&sei->cp_msi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) raw_spin_lock_init(&sei->mask_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sei->base = devm_ioremap_resource(sei->dev, sei->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (IS_ERR(sei->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(sei->dev, "Failed to remap SEI resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return PTR_ERR(sei->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Retrieve the SEI capabilities with the interrupt ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sei->caps = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!sei->caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(sei->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "Could not retrieve controller capabilities\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Reserve the single (top-level) parent SPI IRQ from which all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * interrupts handled by this driver will be signaled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (parent_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Create the root SEI domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sei->sei_domain = irq_domain_create_linear(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (sei->caps->ap_range.size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sei->caps->cp_range.size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &mvebu_sei_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!sei->sei_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(sei->dev, "Failed to create SEI IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto dispose_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) irq_domain_update_bus_token(sei->sei_domain, DOMAIN_BUS_NEXUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Create the 'wired' domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) sei->ap_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) sei->caps->ap_range.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &mvebu_sei_ap_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!sei->ap_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(sei->dev, "Failed to create AP IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto remove_sei_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) irq_domain_update_bus_token(sei->ap_domain, DOMAIN_BUS_WIRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Create the 'MSI' domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sei->cp_domain = irq_domain_create_hierarchy(sei->sei_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sei->caps->cp_range.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &mvebu_sei_cp_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!sei->cp_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pr_err("Failed to create CPs IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto remove_ap_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) irq_domain_update_bus_token(sei->cp_domain, DOMAIN_BUS_GENERIC_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &mvebu_sei_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sei->cp_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!plat_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_err("Failed to create CPs MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto remove_cp_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mvebu_sei_reset(sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mvebu_sei_handle_cascade_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) remove_cp_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) irq_domain_remove(sei->cp_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) remove_ap_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) irq_domain_remove(sei->ap_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) remove_sei_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) irq_domain_remove(sei->sei_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dispose_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) irq_dispose_mapping(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct mvebu_sei_caps mvebu_sei_ap806_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .ap_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .first = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .size = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .cp_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .first = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .size = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct of_device_id mvebu_sei_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .compatible = "marvell,ap806-sei",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .data = &mvebu_sei_ap806_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct platform_driver mvebu_sei_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .probe = mvebu_sei_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "mvebu-sei",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .of_match_table = mvebu_sei_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) builtin_platform_driver(mvebu_sei_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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