Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2017 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Hanna Hawa <hannah@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/jump_label.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <dt-bindings/interrupt-controller/mvebu-icu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* ICU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ICU_SETSPI_NSR_AL	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ICU_SETSPI_NSR_AH	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ICU_CLRSPI_NSR_AL	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ICU_CLRSPI_NSR_AH	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ICU_SET_SEI_AL		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ICU_SET_SEI_AH		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ICU_CLR_SEI_AL		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ICU_CLR_SEI_AH		0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ICU_INT_CFG(x)          (0x100 + 4 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define   ICU_INT_ENABLE	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define   ICU_IS_EDGE		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define   ICU_GROUP_SHIFT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* ICU definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ICU_MAX_IRQS		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ICU_SATA0_ICU_ID	109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ICU_SATA1_ICU_ID	107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct mvebu_icu_subset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int icu_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int offset_set_ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int offset_set_al;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int offset_clr_ah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int offset_clr_al;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct mvebu_icu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct mvebu_icu_msi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mvebu_icu *icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	atomic_t initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	const struct mvebu_icu_subset_data *subset_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) struct mvebu_icu_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct mvebu_icu *icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int icu_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static DEFINE_STATIC_KEY_FALSE(legacy_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void mvebu_icu_init(struct mvebu_icu *icu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			   struct mvebu_icu_msi_data *msi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			   struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const struct mvebu_icu_subset_data *subset = msi_data->subset_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (atomic_cmpxchg(&msi_data->initialized, false, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Set 'SET' ICU SPI message address in AP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	writel_relaxed(msg[0].address_hi, icu->base + subset->offset_set_ah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	writel_relaxed(msg[0].address_lo, icu->base + subset->offset_set_al);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (subset->icu_group != ICU_GRP_NSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* Set 'CLEAR' ICU SPI message address in AP (level-MSI only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	writel_relaxed(msg[1].address_hi, icu->base + subset->offset_clr_ah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct irq_data *d = irq_get_irq_data(desc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct mvebu_icu *icu = icu_irqd->icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned int icu_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (msg->address_lo || msg->address_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/* One off initialization per domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		mvebu_icu_init(icu, msi_data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		/* Configure the ICU with irq number & type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		icu_int = msg->data | ICU_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			icu_int |= ICU_IS_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		/* De-configure the ICU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		icu_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * The SATA unit has 2 ports, and a dedicated ICU entry per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * port. The ahci sata driver supports only one irq interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * per SATA unit. To solve this conflict, we configure the 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * SATA wired interrupts in the south bridge into 1 GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * interrupt in the north bridge. Even if only a single port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * is enabled, if sata node is enabled, both interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * configured (regardless of which port is actually in use).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		writel_relaxed(icu_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			       icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		writel_relaxed(icu_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			       icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct irq_chip mvebu_icu_nsr_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.name			= "ICU-NSR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.irq_set_type		= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct irq_chip mvebu_icu_sei_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.name			= "ICU-SEI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.irq_ack		= irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.irq_set_type		= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			       unsigned long *hwirq, unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct mvebu_icu *icu = platform_msi_get_host_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Check the count of the parameters in dt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (WARN_ON(fwspec->param_count != param_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_err(icu->dev, "wrong ICU parameter count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			fwspec->param_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (static_branch_unlikely(&legacy_bindings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		*hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (fwspec->param[0] != ICU_GRP_NSR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			dev_err(icu->dev, "wrong ICU group type %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				fwspec->param[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		*hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		 * The ICU receives level interrupts. While the NSR are also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		 * level interrupts, SEI are edge interrupts. Force the type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		 * here in this case. Please note that this makes the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		 * handling unreliable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (msi_data->subset_data->icu_group == ICU_GRP_SEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			*type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (*hwirq >= ICU_MAX_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			   unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct irq_fwspec *fwspec = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct mvebu_icu *icu = msi_data->icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct mvebu_icu_irq_data *icu_irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct irq_chip *chip = &mvebu_icu_nsr_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!icu_irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					     &icu_irqd->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(icu->dev, "failed to translate ICU parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto free_irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (static_branch_unlikely(&legacy_bindings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		icu_irqd->icu_group = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		icu_irqd->icu_group = msi_data->subset_data->icu_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	icu_irqd->icu = icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	err = platform_msi_domain_alloc(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto free_irqd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Make sure there is no interrupt left pending by the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		goto free_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (icu_irqd->icu_group == ICU_GRP_SEI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		chip = &mvebu_icu_sei_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					    chip, icu_irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(icu->dev, "failed to set the data to IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		goto free_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) free_msi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	platform_msi_domain_free(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) free_irqd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	kfree(icu_irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			  unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct irq_data *d = irq_get_irq_data(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	kfree(icu_irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	platform_msi_domain_free(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct irq_domain_ops mvebu_icu_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.translate = mvebu_icu_irq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.alloc     = mvebu_icu_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.free      = mvebu_icu_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct mvebu_icu_subset_data mvebu_icu_nsr_subset_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.icu_group = ICU_GRP_NSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.offset_set_ah = ICU_SETSPI_NSR_AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.offset_set_al = ICU_SETSPI_NSR_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.offset_clr_ah = ICU_CLRSPI_NSR_AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.offset_clr_al = ICU_CLRSPI_NSR_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct mvebu_icu_subset_data mvebu_icu_sei_subset_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.icu_group = ICU_GRP_SEI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.offset_set_ah = ICU_SET_SEI_AH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.offset_set_al = ICU_SET_SEI_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct of_device_id mvebu_icu_subset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.compatible = "marvell,cp110-icu-nsr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.data = &mvebu_icu_nsr_subset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.compatible = "marvell,cp110-icu-sei",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.data = &mvebu_icu_sei_subset_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int mvebu_icu_subset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct mvebu_icu_msi_data *msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct device_node *msi_parent_dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	msi_data = devm_kzalloc(dev, sizeof(*msi_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (!msi_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (static_branch_unlikely(&legacy_bindings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		msi_data->icu = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		msi_data->subset_data = &mvebu_icu_nsr_subset_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		msi_data->icu = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		msi_data->subset_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	dev->msi_domain = of_msi_get_domain(dev, dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					    DOMAIN_BUS_PLATFORM_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!dev->msi_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	msi_parent_dn = irq_domain_get_of_node(dev->msi_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!msi_parent_dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 							    mvebu_icu_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 							    &mvebu_icu_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 							    msi_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (!irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		dev_err(dev, "Failed to create ICU MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct platform_driver mvebu_icu_subset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.probe  = mvebu_icu_subset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.name = "mvebu-icu-subset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.of_match_table = mvebu_icu_subset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) builtin_platform_driver(mvebu_icu_subset_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int mvebu_icu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct mvebu_icu *icu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!icu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	icu->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	icu->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (IS_ERR(icu->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		dev_err(&pdev->dev, "Failed to map icu base address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return PTR_ERR(icu->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * Legacy bindings: ICU is one node with one MSI parent: force manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 *                  the probe of the NSR interrupts side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * New bindings: ICU node has children, one per interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 *               having its own MSI parent: call platform_populate().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 * All ICU instances should use the same bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (!of_get_child_count(pdev->dev.of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		static_branch_enable(&legacy_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * Clean all ICU interrupts of type NSR and SEI, required to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * avoid unpredictable SPI assignments done by firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		u32 icu_int, icu_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		icu_int = readl_relaxed(icu->base + ICU_INT_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		icu_grp = icu_int >> ICU_GROUP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (icu_grp == ICU_GRP_NSR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		    (icu_grp == ICU_GRP_SEI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		     !static_branch_unlikely(&legacy_bindings)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	platform_set_drvdata(pdev, icu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (static_branch_unlikely(&legacy_bindings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return mvebu_icu_subset_probe(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return devm_of_platform_populate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct of_device_id mvebu_icu_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ .compatible = "marvell,cp110-icu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct platform_driver mvebu_icu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.probe  = mvebu_icu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		.name = "mvebu-icu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.of_match_table = mvebu_icu_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) builtin_platform_driver(mvebu_icu_driver);