Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2017 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GICP_SETSPI_NSR_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GICP_CLRSPI_NSR_OFFSET	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct mvebu_gicp_spi_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct mvebu_gicp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct mvebu_gicp_spi_range *spi_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	unsigned int spi_ranges_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned int spi_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long *spi_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	spinlock_t spi_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		if (idx < r->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			return r->start + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		idx -= r->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct mvebu_gicp *gicp = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	phys_addr_t clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	msg[0].data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	msg[0].address_lo = lower_32_bits(setspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	msg[0].address_hi = upper_32_bits(setspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	msg[1].data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	msg[1].address_lo = lower_32_bits(clrspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	msg[1].address_hi = upper_32_bits(clrspi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct irq_chip gicp_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.name			= "GICP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.irq_set_type		= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.irq_compose_msi_msg	= gicp_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				 unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct mvebu_gicp *gicp = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	spin_lock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (hwirq == gicp->spi_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		spin_unlock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	__set_bit(hwirq, gicp->spi_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	spin_unlock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	fwspec.param[0] = GIC_SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * Assume edge rising for now, it will be properly set when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * ->set_type() is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		goto free_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					    &gicp_irq_chip, gicp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		goto free_irqs_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) free_irqs_parent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) free_hwirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	spin_lock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	__clear_bit(hwirq, gicp->spi_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	spin_unlock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void gicp_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				 unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct mvebu_gicp *gicp = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (d->hwirq >= gicp->spi_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_lock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__clear_bit(d->hwirq, gicp->spi_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spin_unlock(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct irq_domain_ops gicp_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.alloc	= gicp_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.free	= gicp_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct irq_chip gicp_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name		= "GICP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.irq_set_type	= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.flags		= IRQCHIP_SUPPORTS_LEVEL_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct msi_domain_ops gicp_msi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct msi_domain_info gicp_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		   MSI_FLAG_LEVEL_CAPABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.ops	= &gicp_msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.chip	= &gicp_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int mvebu_gicp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct mvebu_gicp *gicp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct irq_domain *inner_domain, *plat_domain, *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct device_node *irq_parent_dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!gicp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	gicp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	spin_lock_init(&gicp->spi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!gicp->res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	gicp->spi_ranges_cnt = ret / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	gicp->spi_ranges =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			     gicp->spi_ranges_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			     sizeof(struct mvebu_gicp_spi_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (!gicp->spi_ranges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	for (i = 0; i < gicp->spi_ranges_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		of_property_read_u32_index(node, "marvell,spi-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 					   i * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					   &gicp->spi_ranges[i].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		of_property_read_u32_index(node, "marvell,spi-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					   i * 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					   &gicp->spi_ranges[i].count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		gicp->spi_cnt += gicp->spi_ranges[i].count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	gicp->spi_bitmap = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				BITS_TO_LONGS(gicp->spi_cnt), sizeof(long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (!gicp->spi_bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	irq_parent_dn = of_irq_find_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!irq_parent_dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		dev_err(&pdev->dev, "failed to find parent IRQ node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	parent_domain = irq_find_host(irq_parent_dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 						   gicp->spi_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 						   of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 						   &gicp_domain_ops, gicp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (!inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 						     &gicp_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 						     inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (!plat_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		irq_domain_remove(inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	platform_set_drvdata(pdev, gicp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct of_device_id mvebu_gicp_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	{ .compatible = "marvell,ap806-gicp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct platform_driver mvebu_gicp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.probe  = mvebu_gicp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.name = "mvebu-gicp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.of_match_table = mvebu_gicp_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) builtin_platform_driver(mvebu_gicp_driver);