^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Joe.C <yingjoe.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct mtk_sysirq_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 nr_intpol_bases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __iomem **intpol_bases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 *intpol_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 *intpol_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u16 *which_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) irq_hw_number_t hwirq = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mtk_sysirq_chip_data *chip_data = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 intpol_idx = chip_data->intpol_idx[hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 offset, reg_index, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) base = chip_data->intpol_bases[intpol_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg_index = chip_data->which_word[hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) offset = hwirq & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) raw_spin_lock_irqsave(&chip_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) value = readl_relaxed(base + reg_index * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (type == IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) value |= (1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) value &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) writel_relaxed(value, base + reg_index * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) data = data->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = data->chip->irq_set_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) raw_spin_unlock_irqrestore(&chip_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct irq_chip mtk_sysirq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "MT_SYSIRQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .irq_set_type = mtk_sysirq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int mtk_sysirq_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct irq_fwspec gic_fwspec = *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* sysirq doesn't support PPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (fwspec->param[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) &mtk_sysirq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gic_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct irq_domain_ops sysirq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .translate = mtk_sysirq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .alloc = mtk_sysirq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int __init mtk_sysirq_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct irq_domain *domain, *domain_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mtk_sysirq_chip_data *chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret, size, intpol_num = 0, nr_intpol_bases = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) domain_parent = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!domain_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pr_err("mtk_sysirq: interrupt-parent not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!chip_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) while (of_get_address(node, i++, NULL, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) nr_intpol_bases++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (nr_intpol_bases == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_err("mtk_sysirq: base address not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto out_free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) chip_data->intpol_words = kcalloc(nr_intpol_bases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sizeof(*chip_data->intpol_words),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!chip_data->intpol_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto out_free_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) chip_data->intpol_bases = kcalloc(nr_intpol_bases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) sizeof(*chip_data->intpol_bases),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!chip_data->intpol_bases) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto out_free_intpol_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (i = 0; i < nr_intpol_bases; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = of_address_to_resource(node, i, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) intpol_num += size * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chip_data->intpol_words[i] = size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) chip_data->intpol_bases[i] = of_iomap(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret || !chip_data->intpol_bases[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_err("%pOF: couldn't map region %d\n", node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto out_free_intpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) chip_data->intpol_idx = kcalloc(intpol_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sizeof(*chip_data->intpol_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!chip_data->intpol_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto out_free_intpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) chip_data->which_word = kcalloc(intpol_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sizeof(*chip_data->which_word),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!chip_data->which_word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto out_free_intpol_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * assign an index of the intpol_bases for each irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * to set it fast later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (i = 0; i < intpol_num ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 word = i / 32, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (j = 0; word >= chip_data->intpol_words[j] ; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) word -= chip_data->intpol_words[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) chip_data->intpol_idx[i] = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) chip_data->which_word[i] = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &sysirq_domain_ops, chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto out_free_which_word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) raw_spin_lock_init(&chip_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) out_free_which_word:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) kfree(chip_data->which_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) out_free_intpol_idx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) kfree(chip_data->intpol_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) out_free_intpol:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (i = 0; i < nr_intpol_bases; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (chip_data->intpol_bases[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) iounmap(chip_data->intpol_bases[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) kfree(chip_data->intpol_bases);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out_free_intpol_words:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) kfree(chip_data->intpol_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) out_free_chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) kfree(chip_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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