^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Youlin.Pei <youlin.pei@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CIRQ_ACK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CIRQ_MASK_SET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CIRQ_MASK_CLR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CIRQ_SENS_SET 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CIRQ_SENS_CLR 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CIRQ_POL_SET 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CIRQ_POL_CLR 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CIRQ_CONTROL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CIRQ_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CIRQ_EDGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CIRQ_FLUSH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mtk_cirq_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int ext_irq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int ext_irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct mtk_cirq_chip_data *cirq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mtk_cirq_chip_data *chip_data = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int cirq_num = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 mask = 1 << (cirq_num % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void mtk_cirq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mtk_cirq_write_mask(data, CIRQ_MASK_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irq_chip_mask_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void mtk_cirq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mtk_cirq_write_mask(data, CIRQ_MASK_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) irq_chip_unmask_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int mtk_cirq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mtk_cirq_write_mask(data, CIRQ_POL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mtk_cirq_write_mask(data, CIRQ_POL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mtk_cirq_write_mask(data, CIRQ_POL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mtk_cirq_write_mask(data, CIRQ_SENS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mtk_cirq_write_mask(data, CIRQ_POL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mtk_cirq_write_mask(data, CIRQ_SENS_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data = data->parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = data->chip->irq_set_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct irq_chip mtk_cirq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = "MT_CIRQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .irq_mask = mtk_cirq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .irq_unmask = mtk_cirq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .irq_set_type = mtk_cirq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int mtk_cirq_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* cirq support irq number check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (fwspec->param[1] < cirq_data->ext_irq_start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fwspec->param[1] > cirq_data->ext_irq_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *hwirq = fwspec->param[1] - cirq_data->ext_irq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int mtk_cirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct irq_fwspec parent_fwspec = *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = mtk_cirq_domain_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (WARN_ON(nr_irqs != 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &mtk_cirq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct irq_domain_ops cirq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .translate = mtk_cirq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .alloc = mtk_cirq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int mtk_cirq_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 value, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int irq, hwirq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool pending, masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int i, pendret, maskret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * When external interrupts happened, CIRQ will record the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * even CIRQ is not enabled. When execute flush command, CIRQ will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * resend the signals according to the status. So if don't clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * status, CIRQ will resend the wrong signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * arch_suspend_disable_irqs() will be called before CIRQ suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * callback. If clear all the status simply, the external interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * which happened between arch_suspend_disable_irqs and CIRQ suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * callback will be lost. Using following steps to avoid this issue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * - Iterate over all the CIRQ supported interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * - For each interrupt, inspect its pending and masked status at GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * - If pending and unmasked, it happened between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * arch_suspend_disable_irqs and CIRQ suspend callback, don't ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * it. Otherwise, ACK it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) hwirq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < hwirq_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) irq = irq_find_mapping(cirq_data->domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pendret = irq_get_irqchip_state(irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IRQCHIP_STATE_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) maskret = irq_get_irqchip_state(irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IRQCHIP_STATE_MASKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pendret == 0 && maskret == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (pending && !masked))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask = 1 << (i % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* set edge_only mode, record edge-triggerd interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* enable cirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) value |= (CIRQ_EDGE | CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void mtk_cirq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* flush recored interrupts, will send signals to parent controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* disable cirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) value &= ~(CIRQ_EDGE | CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct syscore_ops mtk_cirq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .suspend = mtk_cirq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .resume = mtk_cirq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void mtk_cirq_syscore_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) register_syscore_ops(&mtk_cirq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline void mtk_cirq_syscore_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __init mtk_cirq_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct irq_domain *domain, *domain_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int irq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) domain_parent = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!domain_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err("mtk_cirq: interrupt-parent not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cirq_data = kzalloc(sizeof(*cirq_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!cirq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cirq_data->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!cirq_data->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("mtk_cirq: unable to map cirq register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &cirq_data->ext_irq_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) &cirq_data->ext_irq_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) domain = irq_domain_add_hierarchy(domain_parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) irq_num, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) &cirq_domain_ops, cirq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cirq_data->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mtk_cirq_syscore_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) iounmap(cirq_data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) kfree(cirq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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