^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define INTC_MASK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define INTC_EOI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mst_intc_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int irq_start, nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) bool no_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void mst_set_irq(struct irq_data *d, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mask = 1 << (hwirq % 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) offset += (hwirq / 16) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) raw_spin_lock_irqsave(&cd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) val = readw_relaxed(cd->base + offset) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writew_relaxed(val, cd->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) raw_spin_unlock_irqrestore(&cd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void mst_clear_irq(struct irq_data *d, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mask = 1 << (hwirq % 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) offset += (hwirq / 16) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) raw_spin_lock_irqsave(&cd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = readw_relaxed(cd->base + offset) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writew_relaxed(val, cd->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) raw_spin_unlock_irqrestore(&cd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void mst_intc_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mst_set_irq(d, INTC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void mst_intc_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mst_clear_irq(d, INTC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void mst_intc_eoi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!cd->no_eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mst_set_irq(d, INTC_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct irq_chip mst_intc_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "mst-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .irq_mask = mst_intc_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .irq_unmask = mst_intc_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .irq_eoi = mst_intc_eoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .irq_get_irqchip_state = irq_chip_get_parent_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .irq_set_irqchip_state = irq_chip_set_parent_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .irq_retrigger = irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) IRQCHIP_SKIP_SET_WAKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mst_intc_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mst_intc_chip_data *cd = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (fwspec->param[1] >= cd->nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct irq_fwspec parent_fwspec, *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mst_intc_chip_data *cd = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Not GIC compliant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (fwspec->param[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &mst_intc_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) parent_fwspec = *fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) parent_fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) parent_fwspec.param[1] = cd->irq_start + hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct irq_domain_ops mst_intc_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .translate = mst_intc_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .alloc = mst_intc_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int __init mst_intc_of_init(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct irq_domain *domain, *domain_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct mst_intc_chip_data *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 irq_start, irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) domain_parent = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!domain_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pr_err("mst-intc: interrupt-parent not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cd = kzalloc(sizeof(*cd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cd->base = of_iomap(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!cd->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) kfree(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) raw_spin_lock_init(&cd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cd->irq_start = irq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cd->nr_irqs = irq_end - irq_start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &mst_intc_domain_ops, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) iounmap(cd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) kfree(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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