^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi Ocelot IRQ controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ICPU_CFG_INTR_INTR_STICKY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ICPU_CFG_INTR_INTR_ENA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICPU_CFG_INTR_INTR_ENA_SET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OCELOT_NR_IRQ 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void ocelot_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct irq_chip_type *ct = irq_data_get_chip_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int mask = data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!(val & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *ct->mask_cache &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void ocelot_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct irq_domain *d = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) while (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 hwirq = __fls(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) generic_handle_irq(irq_find_mapping(d, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg &= ~(BIT(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int __init ocelot_irq_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int parent_irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!parent_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) domain = irq_domain_add_linear(node, OCELOT_NR_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_err("%pOFn: unable to add irq domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "icpu", handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pr_err("%pOFn: unable to alloc irq domain gc\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto err_domain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) gc->reg_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!gc->reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_err("%pOFn: unable to map resource\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto err_gc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Mask and ack all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) err_gc_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) irq_free_generic_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) err_domain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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