^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-mmp/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Bin Yang <bin.yang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Haojian Zhuang <haojian.zhuang@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX_ICU_NR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PJ1_INT_SEL 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PJ4_INT_SEL 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SEL_INT_PENDING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SEL_INT_NUM_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct icu_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int virq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int cascade_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *reg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int conf2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int clr_mfp_irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int clr_mfp_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mmp_intc_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int conf2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __iomem *mmp_icu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void __iomem *mmp_icu2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct icu_chip_data icu_data[MAX_ICU_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int max_icu_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern void mmp2_clear_pmic_int(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void icu_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) hwirq = d->irq - data->virq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (data == &icu_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) r = readl_relaxed(mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) r &= ~data->conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) r |= data->conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel_relaxed(r, mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #ifdef CONFIG_CPU_MMP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if ((data->virq_base == data->clr_mfp_irq_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) && (hwirq == data->clr_mfp_hwirq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mmp2_clear_pmic_int();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) r = readl_relaxed(data->reg_mask) | (1 << hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel_relaxed(r, data->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void icu_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) hwirq = d->irq - data->virq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (data == &icu_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) r = readl_relaxed(mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) r &= ~data->conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) r |= data->conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(r, mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (data->conf2_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * ICU1 (above) only controls PJ4 MP1; if using SMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * we need to also mask the MP2 and MM cores via ICU2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) r = readl_relaxed(mmp_icu2_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) r &= ~data->conf2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(r, mmp_icu2_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) r = readl_relaxed(data->reg_mask) | (1 << hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(r, data->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void icu_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) hwirq = d->irq - data->virq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (data == &icu_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) r = readl_relaxed(mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) r &= ~data->conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) r |= data->conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(r, mmp_icu_base + (hwirq << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel_relaxed(r, data->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct irq_chip icu_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "icu_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .irq_mask = icu_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .irq_mask_ack = icu_mask_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .irq_unmask = icu_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void icu_mux_irq_demux(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct icu_chip_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long mask, status, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 1; i < max_icu_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (irq == icu_data[i].cascade_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) domain = icu_data[i].domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) data = (struct icu_chip_data *)domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (i >= max_icu_nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_err("Spurious irq %d in MMP INTC\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mask = readl_relaxed(data->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) status = readl_relaxed(data->reg_status) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for_each_set_bit(n, &status, BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) generic_handle_irq(icu_data[i].virq_base + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct irq_domain_ops mmp_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .map = mmp_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .xlate = mmp_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct mmp_intc_conf mmp_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .conf_enable = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .conf_disable = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .conf_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct mmp_intc_conf mmp2_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .conf_enable = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .conf_disable = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MMP2_ICU_INT_ROUTE_PJ4_FIQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct mmp_intc_conf mmp3_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .conf_enable = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .conf_disable = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MMP2_ICU_INT_ROUTE_PJ4_FIQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .conf2_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!(hwirq & SEL_INT_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hwirq &= SEL_INT_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) handle_domain_irq(icu_data[0].domain, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!(hwirq & SEL_INT_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) hwirq &= SEL_INT_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) handle_domain_irq(icu_data[0].domain, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* MMP (ARMv5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __init icu_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) max_icu_nr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mmp_icu_base = ioremap(0xd4282000, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) icu_data[0].conf_enable = mmp_conf.conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) icu_data[0].conf_disable = mmp_conf.conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) icu_data[0].conf_mask = mmp_conf.conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) icu_data[0].nr_irqs = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) icu_data[0].virq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &icu_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (irq = 0; irq < 64; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) icu_mask_irq(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irq_set_default_host(icu_data[0].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) set_handle_irq(mmp_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* MMP2 (ARMv7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void __init mmp2_init_icu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int irq, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) max_icu_nr = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mmp_icu_base = ioremap(0xd4282000, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) icu_data[0].conf_enable = mmp2_conf.conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) icu_data[0].conf_disable = mmp2_conf.conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) icu_data[0].conf_mask = mmp2_conf.conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) icu_data[0].nr_irqs = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) icu_data[0].virq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &icu_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) icu_data[1].reg_status = mmp_icu_base + 0x150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) icu_data[1].reg_mask = mmp_icu_base + 0x168;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) icu_data[0].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) icu_data[1].nr_irqs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) icu_data[1].cascade_irq = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) icu_data[1].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) &icu_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) icu_data[2].reg_status = mmp_icu_base + 0x154;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) icu_data[2].reg_mask = mmp_icu_base + 0x16c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) icu_data[2].nr_irqs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) icu_data[2].cascade_irq = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) icu_data[2].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &icu_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) icu_data[3].reg_status = mmp_icu_base + 0x180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) icu_data[3].reg_mask = mmp_icu_base + 0x17c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) icu_data[3].nr_irqs = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) icu_data[3].cascade_irq = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) icu_data[3].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &icu_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) icu_data[4].reg_status = mmp_icu_base + 0x158;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) icu_data[4].reg_mask = mmp_icu_base + 0x170;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) icu_data[4].nr_irqs = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) icu_data[4].cascade_irq = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) icu_data[4].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) &icu_data[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) icu_data[5].reg_status = mmp_icu_base + 0x15c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) icu_data[5].reg_mask = mmp_icu_base + 0x174;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) icu_data[5].nr_irqs = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) icu_data[5].cascade_irq = 35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) icu_data[5].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &icu_data[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) icu_data[6].reg_status = mmp_icu_base + 0x160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) icu_data[6].reg_mask = mmp_icu_base + 0x178;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) icu_data[6].nr_irqs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) icu_data[6].cascade_irq = 51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) icu_data[6].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) &icu_data[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) icu_data[7].reg_status = mmp_icu_base + 0x188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) icu_data[7].reg_mask = mmp_icu_base + 0x184;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) icu_data[7].nr_irqs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) icu_data[7].cascade_irq = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) icu_data[7].virq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &irq_domain_simple_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &icu_data[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) end = icu_data[7].virq_base + icu_data[7].nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) for (irq = 0; irq < end; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) icu_mask_irq(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (irq == icu_data[1].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) irq == icu_data[2].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) irq == icu_data[3].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) irq == icu_data[4].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) irq == icu_data[5].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) irq == icu_data[6].cascade_irq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) irq == icu_data[7].cascade_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) irq_set_chip(irq, &icu_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) irq_set_chained_handler(irq, icu_mux_irq_demux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) irq_set_chip_and_handler(irq, &icu_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) irq_set_default_host(icu_data[0].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) set_handle_irq(mmp2_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int __init mmp_init_bases(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret, nr_irqs, irq, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pr_err("Not found mrvl,intc-nr-irqs property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mmp_icu_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!mmp_icu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pr_err("Failed to get interrupt controller register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) icu_data[0].virq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) &mmp_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &icu_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (irq = 0; irq < nr_irqs; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = irq_create_mapping(icu_data[0].domain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pr_err("Failed to mapping hwirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) icu_data[0].virq_base = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) icu_data[0].nr_irqs = nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (icu_data[0].virq_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (i = 0; i < irq; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) irq_dispose_mapping(icu_data[0].virq_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) irq_domain_remove(icu_data[0].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) iounmap(mmp_icu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __init mmp_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = mmp_init_bases(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) icu_data[0].conf_enable = mmp_conf.conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) icu_data[0].conf_disable = mmp_conf.conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) icu_data[0].conf_mask = mmp_conf.conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) set_handle_irq(mmp_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) max_icu_nr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int __init mmp2_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = mmp_init_bases(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) icu_data[0].conf_enable = mmp2_conf.conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) icu_data[0].conf_disable = mmp2_conf.conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) icu_data[0].conf_mask = mmp2_conf.conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) set_handle_irq(mmp2_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) max_icu_nr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int __init mmp3_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mmp_icu2_base = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!mmp_icu2_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pr_err("Failed to get interrupt controller register #2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = mmp_init_bases(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) iounmap(mmp_icu2_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) icu_data[0].conf_enable = mmp3_conf.conf_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) icu_data[0].conf_disable = mmp3_conf.conf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) icu_data[0].conf_mask = mmp3_conf.conf_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) icu_data[0].conf2_mask = mmp3_conf.conf2_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* This is the main interrupt controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) set_handle_irq(mmp2_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) max_icu_nr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) IRQCHIP_DECLARE(mmp3_intc, "marvell,mmp3-intc", mmp3_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int __init mmp2_mux_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int i, ret, irq, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 nr_irqs, mfp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 reg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) i = max_icu_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pr_err("Not found mrvl,intc-nr-irqs property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * For historical reasons, the "regs" property of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * mrvl,mmp2-mux-intc is not a regular "regs" property containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * addresses on the parent bus, but offsets from the intc's base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * That is why we can't use of_address_to_resource() here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = of_property_read_variable_u32_array(node, "reg", reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ARRAY_SIZE(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pr_err("Not found reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) icu_data[i].reg_status = mmp_icu_base + reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) icu_data[i].reg_mask = mmp_icu_base + reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!icu_data[i].cascade_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) icu_data[i].virq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &mmp_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &icu_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (irq = 0; irq < nr_irqs; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = irq_create_mapping(icu_data[i].domain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pr_err("Failed to mapping hwirq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) icu_data[i].virq_base = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) icu_data[i].nr_irqs = nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &mfp_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) icu_data[i].clr_mfp_hwirq = mfp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) irq_set_chained_handler(icu_data[i].cascade_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) icu_mux_irq_demux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) max_icu_nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (icu_data[i].virq_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (j = 0; j < irq; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) irq_dispose_mapping(icu_data[i].virq_base + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) irq_domain_remove(icu_data[i].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags