Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015 Endless Mobile, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define NUM_CHANNEL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX_INPUT_MUX 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_EDGE_POL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_PIN_03_SEL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_PIN_47_SEL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_FILTER_SEL	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* use for A1 like chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_PIN_A1_SEL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * bits 24 to 31. Tests on the actual HW show that these bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * stuck at 0. Bits 8 to 15 are responsive and have the expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_EDGE_POL_EDGE(params, x)	BIT((params)->edge_single_offset + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_EDGE_POL_LOW(params, x)	BIT((params)->pol_low_offset + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_BOTH_EDGE(params, x)	BIT((params)->edge_both_offset + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_EDGE_POL_MASK(params, x)    (	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		REG_EDGE_POL_EDGE(params, x) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		REG_EDGE_POL_LOW(params, x)  |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		REG_BOTH_EDGE(params, x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG_PIN_SEL_SHIFT(x)	(((x) % 4) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_FILTER_SEL_SHIFT(x)	((x) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct meson_gpio_irq_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				    unsigned int channel, unsigned long hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 				      unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				      unsigned long hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct irq_ctl_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				 unsigned int channel, unsigned long hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct meson_gpio_irq_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned int nr_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bool support_edge_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int edge_both_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int edge_single_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int pol_low_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int pin_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct irq_ctl_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define INIT_MESON_COMMON(irqs, init, sel)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.nr_hwirq = irqs,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.ops = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.gpio_irq_init = init,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.gpio_irq_sel_pin = sel,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define INIT_MESON8_COMMON_DATA(irqs)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			  meson8_gpio_irq_sel_pin)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.edge_single_offset = 0,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.pol_low_offset = 16,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.pin_sel_mask = 0xff,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define INIT_MESON_A1_COMMON_DATA(irqs)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			  meson_a1_gpio_irq_sel_pin)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.support_edge_both = true,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.edge_both_offset = 16,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.edge_single_offset = 8,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.pol_low_offset = 0,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.pin_sel_mask = 0x7f,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static const struct meson_gpio_irq_params meson8_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	INIT_MESON8_COMMON_DATA(134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static const struct meson_gpio_irq_params meson8b_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	INIT_MESON8_COMMON_DATA(119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct meson_gpio_irq_params gxbb_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	INIT_MESON8_COMMON_DATA(133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct meson_gpio_irq_params gxl_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	INIT_MESON8_COMMON_DATA(110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct meson_gpio_irq_params axg_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	INIT_MESON8_COMMON_DATA(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct meson_gpio_irq_params sm1_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	INIT_MESON8_COMMON_DATA(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.support_edge_both = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.edge_both_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct meson_gpio_irq_params a1_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	INIT_MESON_A1_COMMON_DATA(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct of_device_id meson_irq_gpio_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct meson_gpio_irq_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	const struct meson_gpio_irq_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32 channel_irqs[NUM_CHANNEL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	DECLARE_BITMAP(channel_map, NUM_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				       unsigned int reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	spin_lock_irqsave(&ctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tmp = readl_relaxed(ctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	tmp |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	writel_relaxed(tmp, ctl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	spin_unlock_irqrestore(&ctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				    unsigned int channel, unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	bit_offset = REG_PIN_SEL_SHIFT(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	meson_gpio_irq_update_bits(ctl, reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				   ctl->params->pin_sel_mask << bit_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				   hwirq << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				      unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				      unsigned long hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned int bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	bit_offset = ((channel % 2) == 0) ? 0 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	meson_gpio_irq_update_bits(ctl, reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				   ctl->params->pin_sel_mask << bit_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				   hwirq << bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* For a1 or later chips like a1 there is a switch to enable/disable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			       unsigned long  hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			       u32 **channel_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spin_lock_irqsave(&ctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* Find a free channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (idx >= NUM_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		spin_unlock_irqrestore(&ctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		pr_err("No channel available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Mark the channel as used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	set_bit(idx, ctl->channel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	spin_unlock_irqrestore(&ctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 * Setup the mux of the channel to route the signal of the pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * to the appropriate input of the GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * Get the hwirq number assigned to this channel through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * a pointer the channel_irq table. The added benifit of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * method is that we can also retrieve the channel index with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * it, using the table base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	*channel_hwirq = &(ctl->channel_irqs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 hwirq, idx, **channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			       u32 *channel_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return channel_hwirq - ctl->channel_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			       u32 *channel_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	clear_bit(idx, ctl->channel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				     unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				     u32 *channel_hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	const struct meson_gpio_irq_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	params = ctl->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * The controller has a filter block to operate in either LEVEL or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 * EDGE_FALLING support (which the GIC does not support), the filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * block is also able to invert the input signal it gets before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * providing it to the GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	type &= IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * New controller support EDGE_BOTH trigger. This setting takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * precedence over the other edge/polarity settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (type == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (!params->support_edge_both)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		val |= REG_BOTH_EDGE(params, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			val |= REG_EDGE_POL_EDGE(params, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			val |= REG_EDGE_POL_LOW(params, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				   REG_EDGE_POL_MASK(params, idx), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static unsigned int meson_gpio_irq_type_output(unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	type &= ~IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * The polarity of the signal provided to the GIC should always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * be high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		type |= IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		type |= IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct meson_gpio_irq_controller *ctl = data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return irq_chip_set_type_parent(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 					meson_gpio_irq_type_output(type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct irq_chip meson_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.name			= "meson-gpio-irqchip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.irq_set_type		= meson_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.flags			= IRQCHIP_SET_TYPE_MASKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 					   struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 					   unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					   unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		*hwirq	= fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		*type	= fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 					   unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 					   u32 hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 					   unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	fwspec.param[0] = 0;	/* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	fwspec.param[1] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	fwspec.param[2] = meson_gpio_irq_type_output(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				       unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 				       unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				       void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct meson_gpio_irq_controller *ctl = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	u32 *channel_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (WARN_ON(nr_irqs != 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 					      *channel_hwirq, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		meson_gpio_irq_release_channel(ctl, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 				      &meson_gpio_irq_chip, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void meson_gpio_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 				       unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 				       unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct meson_gpio_irq_controller *ctl = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u32 *channel_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (WARN_ON(nr_irqs != 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	irq_domain_free_irqs_parent(domain, virq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	irq_data = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	channel_hwirq = irq_data_get_irq_chip_data(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	meson_gpio_irq_release_channel(ctl, channel_hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.alloc		= meson_gpio_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.free		= meson_gpio_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.translate	= meson_gpio_irq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int meson_gpio_irq_parse_dt(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 				   struct meson_gpio_irq_controller *ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	match = of_match_node(meson_irq_gpio_matches, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ctl->params = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	ret = of_property_read_variable_u32_array(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 						  "amlogic,channel-interrupts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 						  ctl->channel_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 						  NUM_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 						  NUM_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ctl->params->ops.gpio_irq_init(ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int meson_gpio_intc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	struct device_node *node = pdev->dev.of_node, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	struct meson_gpio_irq_controller *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	parent = of_irq_find_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		dev_err(&pdev->dev, "missing parent interrupt node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		dev_err(&pdev->dev, "unable to obtain parent domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	ctl = devm_kzalloc(&pdev->dev, sizeof(*ctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (!ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	spin_lock_init(&ctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	ctl->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (IS_ERR(ctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		return PTR_ERR(ctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	ret = meson_gpio_irq_parse_dt(node, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	ctl->domain = irq_domain_create_hierarchy(parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 						  ctl->params->nr_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 						  of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 						  &meson_gpio_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 						  ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (!ctl->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		dev_err(&pdev->dev, "failed to add domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	platform_set_drvdata(pdev, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	dev_info(&pdev->dev, "%d to %d gpio interrupt mux initialized\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		 ctl->params->nr_hwirq, NUM_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int meson_gpio_intc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	struct meson_gpio_irq_controller *ctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	irq_domain_remove(ctl->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct of_device_id meson_gpio_intc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	{ .compatible = "amlogic,meson-gpio-intc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_DEVICE_TABLE(of, meson_gpio_intc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static struct platform_driver meson_gpio_intc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	.probe  = meson_gpio_intc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	.remove = meson_gpio_intc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		.name = "meson-gpio-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		.of_match_table = meson_gpio_intc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_platform_driver(meson_gpio_intc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_ALIAS("platform:meson-gpio-intc");