^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jun Ma <majun258@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Yun Wu <wuyun.wu@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Interrupt numbers per mbigen node supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQS_PER_MBIGEN_NODE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESERVED_IRQ_PER_MBIGEN_CHIP 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* The maximum IRQ pin number of mbigen chip(start from 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAXIMUM_IRQ_PIN_NUM 1407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * In mbigen vector register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * bit[21:12]: event id value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * bit[11:0]: device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IRQ_EVENT_ID_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQ_EVENT_ID_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* register range of each mbigen node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MBIGEN_NODE_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* offset of vector register in mbigen node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_MBIGEN_VEC_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * offset of clear register in mbigen node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * This register is used to clear the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * of interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_MBIGEN_CLEAR_OFFSET 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * offset of interrupt type register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * This register is used to configure interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * trigger type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_MBIGEN_TYPE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct mbigen_device - holds the information of mbigen device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pdev: pointer to the platform device structure of mbigen chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @base: mapped address of this mbigen chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mbigen_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int nid, pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pin = hwirq % IRQS_PER_MBIGEN_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return pin * 4 + nid * MBIGEN_NODE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) + REG_MBIGEN_VEC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 *mask, u32 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int nid, irq_ofst, ofst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *mask = 1 << (irq_ofst % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ofst = irq_ofst / 32 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *addr = ofst + nid * MBIGEN_NODE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) + REG_MBIGEN_TYPE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 *mask, u32 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int ofst = (hwirq / 32) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *mask = 1 << (hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void mbigen_eoi_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *base = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 mask, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) get_mbigen_clear_reg(data->hwirq, &mask, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(mask, base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) irq_chip_eoi_parent(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int mbigen_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *base = data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 mask, addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) get_mbigen_type_reg(data->hwirq, &mask, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = readl_relaxed(base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel_relaxed(val, base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct irq_chip mbigen_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "mbigen-v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .irq_eoi = mbigen_eoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .irq_set_type = mbigen_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct irq_data *d = irq_get_irq_data(desc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void __iomem *base = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!msg->address_lo && !msg->address_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) base += get_mbigen_vec_reg(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val |= (msg->data << IRQ_EVENT_ID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* The address of doorbell is encoded in mbigen register by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * So,we don't need to program the doorbell address at here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel_relaxed(val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int mbigen_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* If there is no valid irq type, just use the default type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int mbigen_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct irq_fwspec *fwspec = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct mbigen_device *mgn_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err = platform_msi_domain_alloc(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mgn_chip = platform_msi_get_host_data(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &mbigen_irq_chip, mgn_chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) platform_msi_domain_free(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct irq_domain_ops mbigen_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .translate = mbigen_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .alloc = mbigen_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .free = mbigen_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int mbigen_of_create_domain(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct mbigen_device *mgn_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct platform_device *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for_each_child_of_node(pdev->dev.of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!of_property_read_bool(np, "interrupt-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) parent = platform_bus_type.dev_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) child = of_platform_device_create(np, NULL, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (of_property_read_u32(child->dev.of_node, "num-pins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) &num_pins) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(&pdev->dev, "No num-pins property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) domain = platform_msi_create_device_domain(&child->dev, num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mbigen_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) &mbigen_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mgn_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int mbigen_acpi_create_domain(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct mbigen_device *mgn_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 num_pins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * "num-pins" is the total number of interrupt pins implemented in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * this mbigen instance, and mbigen is an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * connected to ITS converting wired interrupts into MSI, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * use "num-pins" to alloc MSI vectors which are needed by client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * devices connected to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Here is the DSDT device node used for mbigen in firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Device(MBI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Name(_HID, "HISI0152")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Name(_UID, Zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Name(_CRS, ResourceTemplate() {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Name(_DSD, Package () {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Package () {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Package () {"num-pins", 378}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret || num_pins == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mbigen_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &mbigen_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mgn_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct mbigen_device *mgn_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int mbigen_device_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct mbigen_device *mgn_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!mgn_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mgn_chip->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!mgn_chip->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = mbigen_of_create_domain(pdev, mgn_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else if (ACPI_COMPANION(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err = mbigen_acpi_create_domain(pdev, mgn_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) platform_set_drvdata(pdev, mgn_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct of_device_id mbigen_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .compatible = "hisilicon,mbigen-v2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { /* END */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MODULE_DEVICE_TABLE(of, mbigen_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct acpi_device_id mbigen_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { "HISI0152", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct platform_driver mbigen_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "Hisilicon MBIGEN-V2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .of_match_table = mbigen_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .probe = mbigen_device_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) module_platform_driver(mbigen_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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