^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019, Jiaxun Yang <jiaxun.yang@flygoat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Loongson-1 platform IRQ support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LS_REG_INTC_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LS_REG_INTC_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LS_REG_INTC_SET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LS_REG_INTC_CLR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LS_REG_INTC_POL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LS_REG_INTC_EDGE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * struct ls1x_intc_priv - private ls1x-intc data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @domain: IRQ domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @intc_base: IO Base of intc registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ls1x_intc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *intc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void ls1x_chained_handle_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ls1x_intc_priv *priv = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pending = readl(priv->intc_base + LS_REG_INTC_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) readl(priv->intc_base + LS_REG_INTC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int bit = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) generic_handle_irq(irq_find_mapping(priv->domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pending &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void ls_intc_set_bit(struct irq_chip_generic *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 mask, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel(readl(gc->reg_base + offset) | mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) gc->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(readl(gc->reg_base + offset) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gc->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int ls_intc_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 mask = data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irqd_set_trigger_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return irq_setup_alt_chip(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int __init ls1x_intc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ls1x_intc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int parent_irq, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) priv->intc_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!priv->intc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) goto out_free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_err("ls1x-irq: unable to get parent irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Set up an IRQ domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!priv->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pr_err("ls1x-irq: cannot add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err = irq_alloc_domain_generic_chips(priv->domain, 32, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) node->full_name, handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pr_err("ls1x-irq: unable to register IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Mask all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(0x0, priv->intc_base + LS_REG_INTC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Ack all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Set all irqs to high level triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) gc = irq_get_domain_generic_chip(priv->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gc->reg_base = priv->intc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ct[0].type = IRQ_TYPE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ct[0].regs.mask = LS_REG_INTC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ct[0].regs.ack = LS_REG_INTC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ct[0].chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ct[0].chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ct[0].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ct[0].chip.irq_set_type = ls_intc_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ct[0].handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ct[1].type = IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ct[1].regs.mask = LS_REG_INTC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ct[1].regs.ack = LS_REG_INTC_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ct[1].chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ct[1].chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ct[1].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ct[1].chip.irq_set_type = ls_intc_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ct[1].handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ls1x_chained_handle_irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) iounmap(priv->intc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out_free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IRQCHIP_DECLARE(ls1x_intc, "loongson,ls1x-intc", ls1x_intc_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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