^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LPC32XX_INTC_MASK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LPC32XX_INTC_RAW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC32XX_INTC_STAT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC32XX_INTC_POL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC32XX_INTC_TYPE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC32XX_INTC_FIQ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NR_LPC32XX_IC_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct lpc32xx_irq_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct lpc32xx_irq_chip *lpc32xx_mic_irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return readl_relaxed(ic->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline void lpc32xx_ic_write(struct lpc32xx_irq_chip *ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) writel_relaxed(val, ic->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void lpc32xx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 val, mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void lpc32xx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 val, mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void lpc32xx_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 val, mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool high, edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) edge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) high = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) edge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) high = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) high = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) high = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_info("unsupported irq type %d\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irqd_set_trigger_type(d, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (edge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) while (hwirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irq = __ffs(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) hwirq &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) handle_domain_irq(lpc32xx_mic_irqc->domain, irq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void lpc32xx_sic_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) while (hwirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq = __ffs(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hwirq &= ~BIT(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) generic_handle_irq(irq_find_mapping(ic->domain, irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct lpc32xx_irq_chip *ic = id->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_set_chip_data(virq, ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq_set_status_flags(virq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) irq_set_noprobe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) irq_set_chip_and_handler(virq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .map = lpc32xx_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .unmap = lpc32xx_irq_domain_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int __init lpc32xx_of_ic_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct lpc32xx_irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool is_mic = of_device_is_compatible(node, "nxp,lpc3220-mic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const __be32 *reg = of_get_property(node, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!irqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) irqc->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!irqc->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_err("%pOF: unable to map registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) kfree(irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) irqc->chip.irq_ack = lpc32xx_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irqc->chip.irq_mask = lpc32xx_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) irqc->chip.irq_unmask = lpc32xx_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) irqc->chip.irq_set_type = lpc32xx_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (is_mic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) &lpc32xx_irq_domain_ops, irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!irqc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_err("unable to add irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iounmap(irqc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) kfree(irqc->chip.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) kfree(irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (is_mic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) lpc32xx_mic_irqc = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) set_handle_irq(lpc32xx_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < of_irq_count(node); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) parent_irq = irq_of_parse_and_map(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (parent_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) lpc32xx_sic_handler, irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) lpc32xx_ic_write(irqc, LPC32XX_INTC_MASK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lpc32xx_ic_write(irqc, LPC32XX_INTC_POL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) lpc32xx_ic_write(irqc, LPC32XX_INTC_TYPE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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