^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Loongson PCH MSI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "pch-msi: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct pch_msi_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct mutex msi_map_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) phys_addr_t doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 irq_first; /* The vector number that MSIs starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 num_irqs; /* The number of vectors for MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long *msi_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void pch_msi_mask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void pch_msi_unmask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct irq_chip pch_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .name = "PCH PCI MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .irq_mask = pch_msi_mask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .irq_unmask = pch_msi_unmask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int pch_msi_allocate_hwirq(struct pch_msi_data *priv, int num_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mutex_lock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) first = bitmap_find_free_region(priv->msi_map, priv->num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) get_count_order(num_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (first < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mutex_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mutex_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return priv->irq_first + first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void pch_msi_free_hwirq(struct pch_msi_data *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int hwirq, int num_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int first = hwirq - priv->irq_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mutex_lock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bitmap_release_region(priv->msi_map, first, get_count_order(num_req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mutex_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void pch_msi_compose_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pch_msi_data *priv = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) msg->address_hi = upper_32_bits(priv->doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) msg->address_lo = lower_32_bits(priv->doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) msg->data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct msi_domain_info pch_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .chip = &pch_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct irq_chip middle_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "PCH MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .irq_compose_msi_msg = pch_msi_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int pch_msi_parent_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int virq, int hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) fwspec.param_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fwspec.param[0] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int pch_msi_middle_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pch_msi_data *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int hwirq, err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) hwirq = pch_msi_allocate_hwirq(priv, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (hwirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) err = pch_msi_parent_domain_alloc(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto err_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &middle_irq_chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err_hwirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pch_msi_free_hwirq(priv, hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq_domain_free_irqs_parent(domain, virq, i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void pch_msi_middle_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pch_msi_data *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pch_msi_free_hwirq(priv, d->hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct irq_domain_ops pch_msi_middle_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .alloc = pch_msi_middle_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .free = pch_msi_middle_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int pch_msi_init_domains(struct pch_msi_data *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct irq_domain *middle_domain, *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) priv->num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &pch_msi_middle_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!middle_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pr_err("Failed to create the MSI middle domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) middle_domain->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &pch_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) middle_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pr_err("Failed to create PCI MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) irq_domain_remove(middle_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int pch_msi_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pch_msi_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("Failed to find the parent domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mutex_init(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_err("Failed to allocate resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->doorbell = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (of_property_read_u32(node, "loongson,msi-base-vec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &priv->irq_first)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pr_err("Unable to parse MSI vec base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (of_property_read_u32(node, "loongson,msi-num-vecs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) &priv->num_irqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pr_err("Unable to parse MSI vec number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!priv->msi_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_debug("Registering %d MSIs, starting at %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) priv->num_irqs, priv->irq_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = pch_msi_init_domains(priv, node, parent_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) kfree(priv->msi_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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