^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Loongson Local IO Interrupt Controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <boot_param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LIOINTC_CHIP_IRQ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LIOINTC_NUM_PARENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LIOINTC_INTC_CHIP_START 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LIOINTC_SHIFT_INTx 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LIOINTC_ERRATA_IRQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct liointc_handler_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct liointc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 parent_int_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct liointc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 map_cache[LIOINTC_CHIP_IRQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool has_lpc_irq_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void liointc_chained_handle_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct irq_chip_generic *gc = handler->priv->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Always blame LPC IRQ if we have that bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (handler->priv->has_lpc_irq_errata &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (handler->parent_int_map & gc->mask_cache &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BIT(LIOINTC_ERRATA_IRQ)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pending = BIT(LIOINTC_ERRATA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int bit = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) generic_handle_irq(irq_find_mapping(gc->domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pending &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void liointc_set_bit(struct irq_chip_generic *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 mask, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(readl(gc->reg_base + offset) | mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) gc->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(readl(gc->reg_base + offset) & ~mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gc->reg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int liointc_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 mask = data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq_gc_lock_irqsave(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) irqd_set_trigger_type(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void liointc_resume(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct liointc_priv *priv = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irq_gc_lock_irqsave(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Disable all at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Restore map cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writeb(priv->map_cache[i], gc->reg_base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Restore mask cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int __init liointc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct liointc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 of_parent_int_map[LIOINTC_NUM_PARENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int parent_irq[LIOINTC_NUM_PARENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool have_parent = FALSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int sz, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto out_free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (parent_irq[i] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) have_parent = TRUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!have_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sz = of_property_read_variable_u32_array(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "loongson,parent_int_map",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &of_parent_int_map[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) LIOINTC_NUM_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LIOINTC_NUM_PARENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (sz < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pr_err("loongson-liointc: No parent_int_map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (i = 0; i < LIOINTC_NUM_PARENT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv->handler[i].parent_int_map = of_parent_int_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Setup IRQ domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) domain = irq_domain_add_linear(node, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &irq_generic_chip_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("loongson-liointc: cannot add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err = irq_alloc_domain_generic_chips(domain, 32, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) node->full_name, handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IRQ_NOPROBE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_err("loongson-liointc: unable to register IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Set to level triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writel(0x0, base + LIOINTC_REG_INTC_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Generate parent INT part of map cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 pending = priv->handler[i].parent_int_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int bit = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pending &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Generate core part of map cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writeb(priv->map_cache[i], base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gc->private = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) gc->reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) gc->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) gc->resume = liointc_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ct->chip.irq_set_type = liointc_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gc->mask_cache = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) priv->gc = gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (parent_irq[i] <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) priv->handler[i].priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq_set_chained_handler_and_data(parent_irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) liointc_chained_handle_irq, &priv->handler[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) out_free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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