^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Loongson HyperTransport Interrupt Vector support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "htvec: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HTVEC_EN_OFF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HTVEC_MAX_PARENT_IRQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VEC_COUNT_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct htvec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct irq_domain *htvec_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) raw_spinlock_t htvec_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void htvec_irq_dispatch(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct htvec *priv = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) for (i = 0; i < priv->num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pending = readl(priv->base + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) while (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int bit = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) generic_handle_irq(irq_linear_revmap(priv->htvec_domain, bit +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VEC_COUNT_PER_REG * i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pending &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void htvec_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct htvec *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(BIT(VEC_REG_BIT(d->hwirq)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) priv->base + VEC_REG_IDX(d->hwirq) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void htvec_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct htvec *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spin_lock(&priv->htvec_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) addr = priv->base + HTVEC_EN_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) addr += VEC_REG_IDX(d->hwirq) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg &= ~BIT(VEC_REG_BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) raw_spin_unlock(&priv->htvec_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void htvec_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct htvec *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) raw_spin_lock(&priv->htvec_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) addr = priv->base + HTVEC_EN_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) addr += VEC_REG_IDX(d->hwirq) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg |= BIT(VEC_REG_BIT(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) raw_spin_unlock(&priv->htvec_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct irq_chip htvec_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "LOONGSON_HTVEC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .irq_mask = htvec_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .irq_unmask = htvec_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .irq_ack = htvec_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int type, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct htvec *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) priv, handle_edge_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void htvec_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irq_set_handler(virq + i, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irq_domain_reset_irq_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct irq_domain_ops htvec_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .translate = irq_domain_translate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .alloc = htvec_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .free = htvec_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void htvec_reset(struct htvec *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Clear IRQ cause registers, mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (idx = 0; idx < priv->num_parents; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int htvec_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct htvec *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int err, parent_irq[8], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) raw_spin_lock_init(&priv->htvec_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) priv->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!priv->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto free_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Interrupt may come from any of the 8 interrupt lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) parent_irq[i] = irq_of_parse_and_map(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (parent_irq[i] <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) priv->num_parents++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!priv->num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("Failed to get parent irqs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto iounmap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (VEC_COUNT_PER_REG * priv->num_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &htvec_domain_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!priv->htvec_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pr_err("Failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto irq_dispose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) htvec_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < priv->num_parents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) irq_set_chained_handler_and_data(parent_irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) htvec_irq_dispatch, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irq_dispose:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) irq_dispose_mapping(parent_irq[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) iounmap_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iounmap(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) free_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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