Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * irqchip for the IXP4xx interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on arch/arm/mach-ixp4xx/common.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright 2002 (C) Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2003-2004 (C) MontaVista, Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqchip/irq-ixp4xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IXP4XX_ICPR	0x00 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IXP4XX_ICMR	0x04 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IXP4XX_ICLR	0x08 /* Interrupt IRQ/FIQ Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IXP4XX_ICIP	0x0C /* IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IXP4XX_ICFP	0x10 /* FIQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IXP4XX_ICHR	0x14 /* Interrupt Priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IXP4XX_ICIH	0x18 /* IRQ Highest Pri Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IXP4XX_ICFH	0x1C /* FIQ Highest Pri Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* IXP43x and IXP46x-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	IXP4XX_ICPR2	0x20 /* Interrupt Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	IXP4XX_ICMR2	0x24 /* Interrupt Enable 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	IXP4XX_ICLR2	0x28 /* Interrupt IRQ/FIQ Select 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IXP4XX_ICIP2	0x2C /* IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IXP4XX_ICFP2	0x30 /* FIQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IXP4XX_ICEEN	0x34 /* Error High Pri Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * struct ixp4xx_irq - state container for the Faraday IRQ controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @irqbase: IRQ controller memory base in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * @irqchip: irqchip for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @domain: IRQ domain for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct ixp4xx_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	bool is_356;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Local static state container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static struct ixp4xx_irq ixirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* GPIO Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IXP4XX_GPIO_CLK_0		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IXP4XX_GPIO_CLK_1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* All are level active high (asserted) here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (type != IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void ixp4xx_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (ixi->is_356 && d->hwirq >= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		val &= ~BIT(d->hwirq - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		val &= ~BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Level triggered interrupts on GPIO lines can only be cleared when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * interrupt condition disappears.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void ixp4xx_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ixi->is_356 && d->hwirq >= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		val |= BIT(d->hwirq - 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		val |= BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		__raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct ixp4xx_irq *ixi = &ixirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	for_each_set_bit(i, &status, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		handle_domain_irq(ixi->domain, i, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * IXP465/IXP435 has an upper IRQ status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (ixi->is_356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		for_each_set_bit(i, &status, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			handle_domain_irq(ixi->domain, i + 32, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				       struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				       unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				       unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* We support standard DT translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		*hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		*type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (is_fwnode_irqchip(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		*hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		*type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		WARN_ON(*type == IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				   unsigned int irq, unsigned int nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				   void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct ixp4xx_irq *ixi = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned int type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		 * TODO: after converting IXP4xx to only device tree, set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		 * handle_bad_irq as default handler and assume all consumers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		 * call .set_type() as this is provided in the second cell in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		 * the device tree phandle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		irq_domain_set_info(d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				    irq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				    hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				    &ixi->irqchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				    ixi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				    handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				    NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		irq_set_probe(irq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * This needs to be a hierarchical irqdomain to work well with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * GPIO irqchip (which is lower in the hierarchy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.translate = ixp4xx_irq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.alloc = ixp4xx_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * This function will go away when we transition to DT probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct irq_domain *ixp4xx_get_irq_domain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct ixp4xx_irq *ixi = &ixirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return ixi->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * This is the Linux IRQ to hwirq mapping table. This goes away when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * we have DT support as all IRQ resources are defined in the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * tree. It will register all the IRQs that are not used by the hierarchical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * the GPIO driver using . This is a step-gap solution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct ixp4xx_irq_chunk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.irq = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.hwirq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.nr_irqs = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.irq = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.hwirq = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.nr_irqs = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.irq = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.hwirq = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.nr_irqs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* Only on the 436 variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.irq = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.hwirq = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.nr_irqs = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * @ixi: State container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * @irqbase: Virtual memory base for the interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * @fwnode: Corresponding fwnode abstraction for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __init ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				   void __iomem *irqbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				   struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				   bool is_356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ixi->irqbase = irqbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ixi->is_356 = is_356;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Route all sources to IRQ instead of FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (is_356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		/* Route upper 32 sources to IRQ instead of FIQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		/* Disable upper 32 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		__raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		nr_irqs = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		nr_irqs = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ixi->irqchip.name = "IXP4xx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ixi->irqchip.irq_mask = ixp4xx_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ixi->irqchip.irq_unmask	= ixp4xx_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					       &ixp4xx_irqdomain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 					       ixi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!ixi->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		pr_crit("IXP4XX: can not add primary irqdomain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	set_handle_irq(ixp4xx_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  * @irqbase: physical base for the irq controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void __init ixp4xx_irq_init(resource_size_t irqbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			    bool is_356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct ixp4xx_irq *ixi = &ixirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int nr_chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	base = ioremap(irqbase, 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		pr_crit("IXP4XX: could not ioremap interrupt controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	fwnode = irq_domain_alloc_fwnode(&irqbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		pr_crit("IXP4XX: no domain handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		pr_crit("IXP4XX: failed to set up irqchip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		irq_domain_free_fwnode(fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!is_356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		nr_chunks--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	 * After adding OF support, this is no longer needed: irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 * will be allocated for the respective fwnodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	for (i = 0; i < nr_chunks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			chunk->irq, chunk->irq + chunk->nr_irqs - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		fwspec.fwnode = fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		fwspec.param[0] = chunk->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		ret = __irq_domain_alloc_irqs(ixi->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					      chunk->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 					      chunk->nr_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 					      NUMA_NO_NODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 					      &fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					      false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 					      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EXPORT_SYMBOL_GPL(ixp4xx_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int __init ixp4xx_of_init_irq(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	struct ixp4xx_irq *ixi = &ixirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	bool is_356;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		pr_crit("IXP4XX: could not ioremap interrupt controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	fwnode = of_node_to_fwnode(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* These chip variants have 64 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		of_device_is_compatible(np, "intel,ixp46x-interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		pr_crit("IXP4XX: failed to set up irqchip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		ixp4xx_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		ixp4xx_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		ixp4xx_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		ixp4xx_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif