^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * JZ47xx SoCs TCU IRQ driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/ingenic-tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct ingenic_tcu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int nb_parent_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 parent_irqs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void ingenic_tcu_intc_cascade(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct irq_domain *domain = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regmap *map = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) uint32_t irq_reg, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) regmap_read(map, TCU_REG_TFR, &irq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_read(map, TCU_REG_TMR, &irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) chained_irq_enter(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) irq_reg &= ~irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) for_each_set_bit(i, (unsigned long *)&irq_reg, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) generic_handle_irq(irq_linear_revmap(domain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) chained_irq_exit(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void ingenic_tcu_gc_unmask_enable_reg(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct regmap *map = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap_write(map, ct->regs.ack, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_write(map, ct->regs.enable, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *ct->mask_cache |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void ingenic_tcu_gc_mask_disable_reg(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct regmap *map = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regmap_write(map, ct->regs.disable, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *ct->mask_cache &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void ingenic_tcu_gc_mask_disable_reg_and_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *map = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_write(map, ct->regs.ack, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regmap_write(map, ct->regs.disable, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int __init ingenic_tcu_irq_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct ingenic_tcu *tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret, irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) map = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!tcu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tcu->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_crit("%s: Invalid 'interrupts' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto err_free_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tcu->nb_parent_irqs = irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tcu->domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!tcu->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) goto err_free_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = irq_alloc_domain_generic_chips(tcu->domain, 32, 1, "TCU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) handle_level_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IRQ_NOPROBE | IRQ_LEVEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_crit("%s: Invalid 'interrupts' property\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto out_domain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) gc = irq_get_domain_generic_chip(tcu->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) gc->wake_enabled = IRQ_MSK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) gc->private = tcu->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ct->regs.disable = TCU_REG_TMSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ct->regs.enable = TCU_REG_TMCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ct->regs.ack = TCU_REG_TFCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ct->chip.irq_unmask = ingenic_tcu_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ct->chip.irq_mask = ingenic_tcu_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ct->chip.irq_mask_ack = ingenic_tcu_gc_mask_disable_reg_and_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Mask all IRQs by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regmap_write(tcu->map, TCU_REG_TMSR, IRQ_MSK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * On JZ4740, timer 0 and timer 1 have their own interrupt line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * timers 2-7 share one interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * On SoCs >= JZ4770, timer 5 has its own interrupt line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * timers 0-4 and 6-7 share one single interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * To keep things simple, we just register the same handler to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * all parent interrupts. The handler will properly detect which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * channel fired the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tcu->parent_irqs[i] = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!tcu->parent_irqs[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto out_unmap_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq_set_chained_handler_and_data(tcu->parent_irqs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ingenic_tcu_intc_cascade,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tcu->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) out_unmap_irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) irq_dispose_mapping(tcu->parent_irqs[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) out_domain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_domain_remove(tcu->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) err_free_tcu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) kfree(tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IRQCHIP_DECLARE(jz4760_tcu_irq, "ingenic,jz4760-tcu", ingenic_tcu_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags