Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CTRL_STRIDE_OFF(_t, _r)	(_t * 4 * _r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CHANCTRL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CHANMASK(n, t)		(CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CHANSET(n, t)		(CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CHANSTATUS(n, t)	(CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CHAN_MINTDIS(t)		(CTRL_STRIDE_OFF(t, 3) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CHAN_MASTRSTAT(t)	(CTRL_STRIDE_OFF(t, 3) + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CHAN_MAX_OUTPUT_INT	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct irqsteer_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct clk		*ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int			irq[CHAN_MAX_OUTPUT_INT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int			irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	raw_spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int			reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	int			channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32			*saved_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 				      unsigned long irqnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return (data->reg_num - irqnum / 32 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void imx_irqsteer_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct irqsteer_data *data = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	raw_spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	val |= BIT(d->hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	raw_spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void imx_irqsteer_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct irqsteer_data *data = d->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	raw_spin_lock_irqsave(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	val &= ~BIT(d->hwirq % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	raw_spin_unlock_irqrestore(&data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct irq_chip imx_irqsteer_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.name		= "irqsteer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.irq_mask	= imx_irqsteer_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.irq_unmask	= imx_irqsteer_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	irq_set_status_flags(irq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	irq_set_chip_data(irq, h->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const struct irq_domain_ops imx_irqsteer_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.map		= imx_irqsteer_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.xlate		= irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	for (i = 0; i < data->irq_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (data->irq[i] == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			return i * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void imx_irqsteer_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct irqsteer_data *data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	chained_irq_enter(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	hwirq = imx_irqsteer_get_hwirq_base(data, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (hwirq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		pr_warn("%s: unable to get hwirq base for irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			__func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	for (i = 0; i < 2; i++, hwirq += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		int idx = imx_irqsteer_get_reg_index(data, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		unsigned long irqmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		int pos, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (hwirq >= data->reg_num * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		irqmap = readl_relaxed(data->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				       CHANSTATUS(idx, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		for_each_set_bit(pos, &irqmap, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			virq = irq_find_mapping(data->domain, pos + hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	chained_irq_exit(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int imx_irqsteer_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct irqsteer_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 irqs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	data->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (IS_ERR(data->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_err(&pdev->dev, "failed to initialize reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return PTR_ERR(data->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (IS_ERR(data->ipg_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				     "failed to get ipg clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	raw_spin_lock_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = of_property_read_u32(np, "fsl,channel", &data->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * There is one output irq for each group of 64 inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * One register bit map can represent 32 input interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	data->irq_count = DIV_ROUND_UP(irqs_num, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	data->reg_num = irqs_num / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		data->saved_reg = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					sizeof(u32) * data->reg_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (!data->saved_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = clk_prepare_enable(data->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* steer all IRQs into configured channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	data->domain = irq_domain_add_linear(np, data->reg_num * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 					     &imx_irqsteer_domain_ops, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!data->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dev_err(&pdev->dev, "failed to create IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	for (i = 0; i < data->irq_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		data->irq[i] = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (!data->irq[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		irq_set_chained_handler_and_data(data->irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 						 imx_irqsteer_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 						 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	clk_disable_unprepare(data->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int imx_irqsteer_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	for (i = 0; i < irqsteer_data->irq_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		irq_set_chained_handler_and_data(irqsteer_data->irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 						 NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	irq_domain_remove(irqsteer_data->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	clk_disable_unprepare(irqsteer_data->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void imx_irqsteer_save_regs(struct irqsteer_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	for (i = 0; i < data->reg_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		data->saved_reg[i] = readl_relaxed(data->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 						CHANMASK(i, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	for (i = 0; i < data->reg_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		writel_relaxed(data->saved_reg[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			       data->regs + CHANMASK(i, data->reg_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int imx_irqsteer_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	imx_irqsteer_save_regs(irqsteer_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	clk_disable_unprepare(irqsteer_data->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int imx_irqsteer_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ret = clk_prepare_enable(irqsteer_data->ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		dev_err(dev, "failed to enable ipg clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	imx_irqsteer_restore_regs(irqsteer_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct dev_pm_ops imx_irqsteer_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct of_device_id imx_irqsteer_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ .compatible = "fsl,imx-irqsteer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct platform_driver imx_irqsteer_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.name = "imx-irqsteer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.of_match_table = imx_irqsteer_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.pm = &imx_irqsteer_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.probe = imx_irqsteer_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.remove = imx_irqsteer_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) builtin_platform_driver(imx_irqsteer_driver);