^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG PowerDown Controller (PDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010-2013 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Exposes the syswake and PDC peripheral wake interrupts to the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* PDC interrupt register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PDC_IRQ_STATUS 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PDC_IRQ_ENABLE 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PDC_IRQ_CLEAR 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PDC_IRQ_ROUTE 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PDC_SYS_WAKE_BASE 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDC_SYS_WAKE_STRIDE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDC_SYS_WAKE_CONFIG_BASE 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PDC_SYS_WAKE_CONFIG_STRIDE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PDC interrupt register field masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PDC_IRQ_SYS3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PDC_IRQ_SYS2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PDC_IRQ_SYS1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PDC_IRQ_SYS0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PDC_IRQ_ROUTE_WU_EN_SYS3 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PDC_IRQ_ROUTE_WU_EN_SYS2 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PDC_IRQ_ROUTE_WU_EN_SYS1 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PDC_IRQ_ROUTE_WU_EN_SYS0 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PDC_IRQ_ROUTE_WU_EN_WD 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PDC_IRQ_ROUTE_WU_EN_IR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PDC_IRQ_ROUTE_WU_EN_RTC 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PDC_IRQ_ROUTE_EXT_EN_SYS3 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PDC_IRQ_ROUTE_EXT_EN_SYS2 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PDC_IRQ_ROUTE_EXT_EN_SYS1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PDC_IRQ_ROUTE_EXT_EN_SYS0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PDC_IRQ_ROUTE_EXT_EN_WD 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PDC_IRQ_ROUTE_EXT_EN_IR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PDC_IRQ_ROUTE_EXT_EN_RTC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PDC_SYS_WAKE_RESET 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PDC_SYS_WAKE_INT_MODE 0x0000000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PDC_SYS_WAKE_INT_MODE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PDC_SYS_WAKE_PIN_VAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* PDC interrupt constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PDC_SYS_WAKE_INT_LOW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PDC_SYS_WAKE_INT_HIGH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PDC_SYS_WAKE_INT_DOWN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PDC_SYS_WAKE_INT_UP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PDC_SYS_WAKE_INT_CHANGE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PDC_SYS_WAKE_INT_NONE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * struct pdc_intc_priv - private pdc interrupt data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @nr_perips: Number of peripheral interrupt signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @nr_syswakes: Number of syswake signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @perip_irqs: List of peripheral IRQ numbers handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @syswake_irq: Shared PDC syswake IRQ number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @domain: IRQ domain for PDC peripheral and syswake IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @pdc_base: Base of PDC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @irq_route: Cached version of PDC_IRQ_ROUTE register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @lock: Lock to protect the PDC syswake registers and the cached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * values of those registers in this struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pdc_intc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int nr_perips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int nr_syswakes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int *perip_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int syswake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *pdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 irq_route;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) iowrite32(data, priv->pdc_base + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static unsigned int pdc_read(struct pdc_intc_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int reg_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ioread32(priv->pdc_base + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Generic IRQ callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SYS0_HWIRQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned int hwirq_is_syswake(irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return hw >= SYS0_HWIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned int hwirq_to_syswake(irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return hw - SYS0_HWIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static irq_hw_number_t syswake_to_hwirq(unsigned int syswake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return SYS0_HWIRQ + syswake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct pdc_intc_priv *irqd_to_priv(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return (struct pdc_intc_priv *)data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * wake bits, therefore we cannot use the generic irqchip mask callbacks as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * cache the mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void perip_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pdc_intc_priv *priv = irqd_to_priv(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) raw_spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) priv->irq_route &= ~data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) raw_spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void perip_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pdc_intc_priv *priv = irqd_to_priv(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) raw_spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) priv->irq_route |= data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) raw_spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pdc_intc_priv *priv = irqd_to_priv(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int syswake = hwirq_to_syswake(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int irq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int soc_sys_wake_regoff, soc_sys_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* translate to syswake IRQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) irq_mode = PDC_SYS_WAKE_INT_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq_mode = PDC_SYS_WAKE_INT_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) irq_mode = PDC_SYS_WAKE_INT_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) irq_mode = PDC_SYS_WAKE_INT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) irq_mode = PDC_SYS_WAKE_INT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* set the IRQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) soc_sys_wake |= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* and update the handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) irq_setup_alt_chip(data, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) raw_spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* applies to both peripheral and syswake interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int pdc_irq_set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pdc_intc_priv *priv = irqd_to_priv(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irq_hw_number_t hw = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int mask = (1 << 16) << hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int dst_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) raw_spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->irq_route |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->irq_route &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) raw_spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* control the destination IRQ wakeup too for standby mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (hwirq_is_syswake(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dst_irq = priv->syswake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dst_irq = priv->perip_irqs[hw];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq_set_irq_wake(dst_irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void pdc_intc_perip_isr(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct pdc_intc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int i, irq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* find the peripheral number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < priv->nr_perips; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (irq == priv->perip_irqs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* should never get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* pass on the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) irq_no = irq_linear_revmap(priv->domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) generic_handle_irq(irq_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void pdc_intc_syswake_isr(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct pdc_intc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int syswake, irq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) status = pdc_read(priv, PDC_IRQ_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pdc_read(priv, PDC_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) status &= (1 << priv->nr_syswakes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) for (syswake = 0; status; status >>= 1, ++syswake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Has this sys_wake triggered? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!(status & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) irq_no = irq_linear_revmap(priv->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) syswake_to_hwirq(syswake));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) generic_handle_irq(irq_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void pdc_intc_setup(struct pdc_intc_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int soc_sys_wake_regoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int soc_sys_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Mask all syswake interrupts before routing, or we could receive an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * interrupt before we're ready to handle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pdc_write(priv, PDC_IRQ_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Enable routing of all syswakes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Disable all wake sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PDC_IRQ_ROUTE_EXT_EN_SYS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Initialise syswake IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (i = 0; i < priv->nr_syswakes; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* set the IRQ mode to none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) soc_sys_wake = PDC_SYS_WAKE_INT_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) << PDC_SYS_WAKE_INT_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int pdc_intc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct pdc_intc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct resource *res_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Get registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (res_regs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(&pdev->dev, "cannot find registers resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Allocate driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(&pdev->dev, "cannot allocate device data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) raw_spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Ioremap the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) resource_size(res_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!priv->pdc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Get number of peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = of_property_read_u32(node, "num-perips", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(&pdev->dev, "No num-perips node property found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (val > SYS0_HWIRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(&pdev->dev, "num-perips (%u) out of range\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) priv->nr_perips = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Get number of syswakes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = of_property_read_u32(node, "num-syswakes", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(&pdev->dev, "No num-syswakes node property found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (val > SYS0_HWIRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) priv->nr_syswakes = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Get peripheral IRQ numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->perip_irqs = devm_kcalloc(&pdev->dev, 4, priv->nr_perips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!priv->perip_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(&pdev->dev, "cannot allocate perip IRQ list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < priv->nr_perips; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) irq = platform_get_irq(pdev, 1 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->perip_irqs[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* check if too many were provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (platform_get_irq(pdev, 1 + i) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(&pdev->dev, "surplus perip IRQs detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Get syswake IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) priv->syswake_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Set up an IRQ domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (unlikely(!priv->domain)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(&pdev->dev, "cannot add IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Set up 2 generic irq chips with 2 chip types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * The first one for peripheral irqs (only 1 chip type used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * The second one for syswake irqs (edge and level chip types)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) handle_level_irq, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) IRQ_GC_INIT_NESTED_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto err_generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* peripheral interrupt chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) gc = irq_get_domain_generic_chip(priv->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) gc->unused = ~(BIT(priv->nr_perips) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gc->reg_base = priv->pdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * IRQ_ROUTE contains wake bits, so we can't use the generic versions as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * they cache the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gc->chip_types[0].chip.irq_mask = perip_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) gc->chip_types[0].chip.irq_unmask = perip_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* syswake interrupt chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gc = irq_get_domain_generic_chip(priv->domain, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) gc->unused = ~(BIT(priv->nr_syswakes) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gc->reg_base = priv->pdc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) gc->chip_types[0].handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* for standby we pass on to the shared syswake IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* level interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) gc->chip_types[1].handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* for standby we pass on to the shared syswake IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Set up the hardware to enable interrupt routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pdc_intc_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Setup chained handlers for the peripheral IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; i < priv->nr_perips; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) irq = priv->perip_irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Setup chained handler for the syswake IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) irq_set_chained_handler_and_data(priv->syswake_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pdc_intc_syswake_isr, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) priv->nr_perips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) priv->nr_syswakes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) err_generic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int pdc_intc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct pdc_intc_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct of_device_id pdc_intc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { .compatible = "img,pdc-intc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct platform_driver pdc_intc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "pdc-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .of_match_table = pdc_intc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .probe = pdc_intc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .remove = pdc_intc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int __init pdc_intc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return platform_driver_register(&pdc_intc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) core_initcall(pdc_intc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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