Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hisilicon HiP04 INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2002-2014 ARM Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2013-2014 Hisilicon Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2013-2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Interrupt architecture for the HIP04 INTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * o There is one Interrupt Distributor, which receives interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   from system devices and sends them to the Interrupt Controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * o There is one CPU Interface per CPU, which sends interrupts sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *   by the Distributor, and interrupts generated locally, to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *   associated CPU. The base address of the CPU interface is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   aliased so that the same address points to different chips depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *   on the CPU it is accessed from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Note that IRQs 0-31 are special - they are local to each CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * As such, the enable set/clear, pending set/clear and active bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * registers are banked per-cpu for these sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include "irq-gic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HIP04_MAX_IRQS		510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct hip04_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static DEFINE_RAW_SPINLOCK(irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * The GIC mapping of CPU interfaces does not necessarily match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * the logical CPU numbering.  Let's use a mapping as returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * by the GIC itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define NR_HIP04_CPU_IF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static struct hip04_irq_data hip04_data __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static inline void __iomem *hip04_dist_base(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return hip04_data->dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static inline void __iomem *hip04_cpu_base(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return hip04_data->cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline unsigned int hip04_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * Routines to acknowledge, disable and enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void hip04_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 mask = 1 << (hip04_irq(d) % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	raw_spin_lock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		       (hip04_irq(d) / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	raw_spin_unlock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void hip04_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 mask = 1 << (hip04_irq(d) % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	raw_spin_lock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		       (hip04_irq(d) / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	raw_spin_unlock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void hip04_eoi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int hip04_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	void __iomem *base = hip04_dist_base(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int irq = hip04_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Interrupt configuration for SGIs can't be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (irq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* SPIs have restrictions on the supported types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			 type != IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	raw_spin_lock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (ret && irq < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* Misconfigured PPIs are usually not fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	raw_spin_unlock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int hip04_irq_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				  const struct cpumask *mask_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				  bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned int cpu, shift = (hip04_irq(d) % 2) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 val, mask, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (!force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		cpu = cpumask_any_and(mask_val, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		cpu = cpumask_first(mask_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	raw_spin_lock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	mask = 0xffff << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bit = hip04_cpu_map[cpu] << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	val = readl_relaxed(reg) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	writel_relaxed(val | bit, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	raw_spin_unlock(&irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return IRQ_SET_MASK_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void hip04_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned long flags, map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	raw_spin_lock_irqsave(&irq_controller_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* Convert our logical CPU mask into a physical one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	for_each_cpu(cpu, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		map |= hip04_cpu_map[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * Ensure that stores to Normal memory are visible to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * other CPUs before they observe us issuing the IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	dmb(ishst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* this always happens on GIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 irqstat, irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	void __iomem *cpu_base = hip04_data.cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (irqnr <= HIP04_MAX_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			handle_domain_irq(hip04_data.domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	} while (irqnr > HIP04_MAX_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct irq_chip hip04_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.name			= "HIP04 INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.irq_mask		= hip04_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.irq_unmask		= hip04_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.irq_eoi		= hip04_eoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.irq_set_type		= hip04_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.irq_set_affinity	= hip04_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.ipi_send_mask		= hip04_ipi_send_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.flags			= IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				  IRQCHIP_SKIP_SET_WAKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				  IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u16 hip04_get_cpumask(struct hip04_irq_data *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	void __iomem *base = intc->dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u32 mask, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	for (i = mask = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		mask |= mask >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __init hip04_irq_dist_init(struct hip04_irq_data *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u32 cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned int nr_irqs = intc->nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	void __iomem *base = intc->dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	writel_relaxed(0, base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * Set all global interrupts to this CPU only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	cpumask = hip04_get_cpumask(intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	cpumask |= cpumask << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	for (i = 32; i < nr_irqs; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	gic_dist_config(base, nr_irqs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	writel_relaxed(1, base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void hip04_irq_cpu_init(struct hip04_irq_data *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	void __iomem *dist_base = intc->dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	void __iomem *base = intc->cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	unsigned int cpu_mask, cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * Get what the GIC says our CPU mask is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	BUG_ON(cpu >= NR_HIP04_CPU_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	cpu_mask = hip04_get_cpumask(intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	hip04_cpu_map[cpu] = cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * Clear our mask from the other map entries in case they're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 * still undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	for (i = 0; i < NR_HIP04_CPU_IF; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (i != cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			hip04_cpu_map[i] &= ~cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	gic_cpu_config(dist_base, 32, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	writel_relaxed(1, base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (hw < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					 handle_percpu_devid_fasteoi_ipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	} else if (hw < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					 handle_percpu_devid_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					 handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	irq_set_chip_data(irq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int hip04_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				  struct device_node *controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				  const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				  unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				  unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (irq_domain_get_of_node(d) != controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (intsize == 1 && intspec[0] < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		*out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		*out_type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (intsize < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	/* Get the interrupt number and add 16 to skip over SGIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	*out_hwirq = intspec[1] + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* For SPIs, we need to add 16 more to get the irq ID number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (!intspec[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		*out_hwirq += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int hip04_irq_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	hip04_irq_cpu_init(&hip04_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct irq_domain_ops hip04_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.map	= hip04_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.xlate	= hip04_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) hip04_of_init(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int nr_irqs, irq_base, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (WARN_ON(!node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	hip04_data.dist_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	hip04_data.cpu_base = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 * Initialize the CPU interface map to all CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 * It will be refined as each CPU probes its ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	for (i = 0; i < NR_HIP04_CPU_IF; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		hip04_cpu_map[i] = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * Find out how many interrupts are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * The HIP04 INTC only supports up to 510 interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	nr_irqs = (nr_irqs + 1) * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (nr_irqs > HIP04_MAX_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		nr_irqs = HIP04_MAX_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	hip04_data.nr_irqs = nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		pr_err("failed to allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 						  0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 						  &hip04_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 						  &hip04_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (WARN_ON(!hip04_data.domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	set_smp_ipi_range(irq_base, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	set_handle_irq(hip04_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	hip04_irq_dist_init(&hip04_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	cpuhp_setup_state(CPUHP_AP_IRQ_HIP04_STARTING, "irqchip/hip04:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			  hip04_irq_starting_cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);