^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 ARM Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Interrupt architecture for the GIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * o There is one Interrupt Distributor, which receives interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * from system devices and sends them to the Interrupt Controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * o There is one CPU Interface per CPU, which sends interrupts sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * by the Distributor, and interrupts generated locally, to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * associated CPU. The base address of the CPU interface is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * aliased so that the same address points to different chips depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * on the CPU it is accessed from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Note that IRQs 0-31 are special - they are local to each CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * As such, the enable set/clear, pending set/clear and active bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * registers are banked per-cpu for these sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/virt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "irq-gic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void gic_check_cpu_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) TAINT_CPU_OUT_OF_SPEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "GICv3 system registers enabled, broken firmware!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define gic_check_cpu_features() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) union gic_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *common_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __percpu * __iomem *percpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct gic_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) union gic_base dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) union gic_base cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *raw_dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *raw_cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 percpu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 __percpu *saved_ppi_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 __percpu *saved_ppi_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 __percpu *saved_ppi_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifdef CONFIG_BL_SWITCHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static DEFINE_RAW_SPINLOCK(cpu_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define gic_lock_irqsave(f) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) raw_spin_lock_irqsave(&cpu_map_lock, (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define gic_unlock_irqrestore(f) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define gic_lock() raw_spin_lock(&cpu_map_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define gic_unlock() raw_spin_unlock(&cpu_map_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define gic_lock_irqsave(f) do { (void)(f); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define gic_lock() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define gic_unlock() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The GIC mapping of CPU interfaces does not necessarily match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * the logical CPU numbering. Let's use a mapping as returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * by the GIC itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NR_GIC_CPU_IF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct gic_kvm_info gic_v2_kvm_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static DEFINE_PER_CPU(u32, sgi_intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_GIC_NON_BANKED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static DEFINE_STATIC_KEY_FALSE(frankengic_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void enable_frankengic(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static_branch_enable(&frankengic_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void __iomem *__get_base(union gic_base *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (static_branch_unlikely(&frankengic_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return raw_cpu_read(*base->percpu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return base->common_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define gic_data_dist_base(d) __get_base(&(d)->dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define gic_data_dist_base(d) ((d)->dist_base.common_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define enable_frankengic() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline void __iomem *gic_dist_base(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return gic_data_dist_base(gic_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline void __iomem *gic_cpu_base(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return gic_data_cpu_base(gic_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline unsigned int gic_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline bool cascading_gic_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void *data = irq_data_get_irq_handler_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * If handler_data is set, this is a cascading interrupt, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * it cannot possibly be forwarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return data != NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Routines to acknowledge, disable and enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void gic_poke_irq(struct irq_data *d, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 mask = 1 << (gic_irq(d) % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int gic_peek_irq(struct irq_data *d, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 mask = 1 << (gic_irq(d) % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void gic_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void gic_eoimode1_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) gic_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * When masking a forwarded interrupt, make sure it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * deactivated as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * This ensures that an interrupt that is getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * disabled/masked will not get "stuck", because there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * noone to deactivate it (guest is being terminated).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (irqd_is_forwarded_to_vcpu(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void gic_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) gic_poke_irq(d, GIC_DIST_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void gic_eoi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 hwirq = gic_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (hwirq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hwirq = this_cpu_read(sgi_intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void gic_eoimode1_eoi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 hwirq = gic_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Do not deactivate an IRQ forwarded to a vcpu. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (irqd_is_forwarded_to_vcpu(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (hwirq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) hwirq = this_cpu_read(sgi_intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int gic_irq_set_irqchip_state(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum irqchip_irq_state which, bool val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case IRQCHIP_STATE_PENDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case IRQCHIP_STATE_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case IRQCHIP_STATE_MASKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) gic_poke_irq(d, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int gic_irq_get_irqchip_state(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum irqchip_irq_state which, bool *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case IRQCHIP_STATE_PENDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case IRQCHIP_STATE_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case IRQCHIP_STATE_MASKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int gic_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void __iomem *base = gic_dist_base(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int gicirq = gic_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Interrupt configuration for SGIs can't be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (gicirq < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* SPIs have restrictions on the supported types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) type != IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret && gicirq < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Misconfigured PPIs are usually not fatal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (cascading_gic_irq(d) || gic_irq(d) < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) irqd_set_forwarded_to_vcpu(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) irqd_clr_forwarded_to_vcpu(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int gic_retrigger(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 irqstat, irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct gic_chip_data *gic = &gic_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *cpu_base = gic_data_cpu_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) irqstat = readl_relaxed(cpu_base + GIC_CPU_ALIAS_INTACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) irqnr = irqstat & GICC_IAR_INT_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (unlikely(irqnr >= 1020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (static_branch_likely(&supports_deactivate_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Ensure any shared data written by the CPU sending the IPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * is read after we've read the ACK register on the GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Pairs with the write barrier in gic_ipi_send_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (irqnr <= 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) smp_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * The GIC encodes the source CPU in GICC_IAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * leading to the deactivation to fail if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * written back as is to GICC_EOI. Stash the INTID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * away for gic_eoi_irq() to write back. This only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * works because we don't nest SGIs...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) this_cpu_write(sgi_intid, irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) handle_domain_irq(gic->domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void gic_handle_cascade_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int cascade_irq, gic_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_ALIAS_INTACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) gic_irq = (status & GICC_IAR_INT_ID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (gic_irq == GICC_INT_SPURIOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) handle_bad_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) generic_handle_irq(cascade_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct irq_chip gic_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .irq_mask = gic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .irq_unmask = gic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .irq_eoi = gic_eoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .irq_set_type = gic_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .irq_retrigger = gic_retrigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .irq_get_irqchip_state = gic_irq_get_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .irq_set_irqchip_state = gic_irq_set_irqchip_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .flags = IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) IRQCHIP_SKIP_SET_WAKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &gic_data[gic_nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static u8 gic_get_cpumask(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __iomem *base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 mask, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = mask = 0; i < 32; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mask = readl_relaxed(base + GIC_DIST_TARGET + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mask |= mask >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mask |= mask >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!mask && num_possible_cpus() > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static bool gic_check_gicv2(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 val = readl_relaxed(base + GIC_CPU_IDENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return (val & 0xff0fff) == 0x02043B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void gic_cpu_if_up(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __iomem *cpu_base = gic_data_cpu_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 bypass = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mode = GIC_CPU_CTRL_EOImodeNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (gic_check_gicv2(cpu_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Preserve bypass disable bits to be written back later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bypass = readl(cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bypass &= GICC_DIS_BYPASS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) writel_relaxed(0x0f, cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void gic_dist_init(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int gic_irqs = gic->gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void __iomem *base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Set all global interrupts to this CPU only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cpumask = gic_get_cpumask(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cpumask |= cpumask << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cpumask |= cpumask << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) for (i = 32; i < gic_irqs; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) gic_dist_config(base, gic_irqs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* set all the interrupt to non-secure state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < gic_irqs; i += 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel_relaxed(0xffffffff, base + GIC_DIST_IGROUP + i * 4 / 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dsb(sy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel_relaxed(3, base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int gic_cpu_init(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void __iomem *dist_base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void __iomem *base = gic_data_cpu_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int cpu_mask, cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Setting up the CPU map is only relevant for the primary GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * because any nested/secondary GICs do not directly interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * with the CPU(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (gic == &gic_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Get what the GIC says our CPU mask is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (WARN_ON(cpu >= NR_GIC_CPU_IF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) gic_check_cpu_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cpu_mask = gic_get_cpumask(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) gic_cpu_map[cpu] = cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Clear our mask from the other map entries in case they're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * still undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < NR_GIC_CPU_IF; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (i != cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) gic_cpu_map[i] &= ~cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gic_cpu_config(dist_base, 32, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) gic_cpu_if_up(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int gic_cpu_if_down(unsigned int gic_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) void __iomem *cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val = readl(cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val &= ~GICC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Saves the GIC distributor registers during suspend or idle. Must be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * with interrupts disabled but before powering down the GIC. After calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * this function, no interrupts will be delivered by the GIC, and another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * platform-specific wakeup source must be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void gic_dist_save(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (WARN_ON(!gic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) gic_irqs = gic->gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dist_base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) gic->saved_spi_conf[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) gic->saved_spi_target[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) gic->saved_spi_enable[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) gic->saved_spi_active[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Restores the GIC distributor registers during resume or when coming out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * idle. Must be called before enabling interrupts. If a level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * that occurred while the GIC was suspended is still present, it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * handled normally, but any edge interrupts that occurred will not be seen by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * the GIC and need to be handled by the platform-specific wakeup source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) void gic_dist_restore(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (WARN_ON(!gic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) gic_irqs = gic->gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dist_base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) writel_relaxed(gic->saved_spi_conf[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dist_base + GIC_DIST_CONFIG + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) writel_relaxed(GICD_INT_DEF_PRI_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dist_base + GIC_DIST_PRI + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel_relaxed(gic->saved_spi_target[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dist_base + GIC_DIST_TARGET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) writel_relaxed(gic->saved_spi_enable[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dist_base + GIC_DIST_ENABLE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel_relaxed(gic->saved_spi_active[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dist_base + GIC_DIST_ACTIVE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) writel_relaxed(3, dist_base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) void gic_cpu_save(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void __iomem *cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (WARN_ON(!gic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dist_base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) cpu_base = gic_data_cpu_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!dist_base || !cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ptr = raw_cpu_ptr(gic->saved_ppi_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ptr = raw_cpu_ptr(gic->saved_ppi_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ptr = raw_cpu_ptr(gic->saved_ppi_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) void gic_cpu_restore(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) void __iomem *cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (WARN_ON(!gic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dist_base = gic_data_dist_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cpu_base = gic_data_cpu_base(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!dist_base || !cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ptr = raw_cpu_ptr(gic->saved_ppi_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ptr = raw_cpu_ptr(gic->saved_ppi_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ptr = raw_cpu_ptr(gic->saved_ppi_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) writel_relaxed(GICD_INT_DEF_PRI_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dist_base + GIC_DIST_PRI + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) gic_cpu_if_up(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case CPU_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) gic_cpu_save(&gic_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case CPU_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case CPU_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) gic_cpu_restore(&gic_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) gic_dist_save(&gic_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case CPU_CLUSTER_PM_ENTER_FAILED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gic_dist_restore(&gic_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static struct notifier_block gic_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .notifier_call = gic_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int gic_pm_init(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (WARN_ON(!gic->saved_ppi_enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (WARN_ON(!gic->saved_ppi_active))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto free_ppi_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (WARN_ON(!gic->saved_ppi_conf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto free_ppi_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (gic == &gic_data[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) cpu_pm_register_notifier(&gic_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) free_ppi_active:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) free_percpu(gic->saved_ppi_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) free_ppi_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) free_percpu(gic->saved_ppi_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int gic_pm_init(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * ICDISR each bit 0 -- Secure 1--Non-Secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) void gic_set_irq_secure(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void __iomem *base = gic_dist_base(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) base += GIC_DIST_IGROUP + ((gic_irq(d) / 32) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mask = readl_relaxed(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mask &= ~(1 << (gic_irq(d) % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) writel_relaxed(mask, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) void gic_set_irq_priority(struct irq_data *d, u8 pri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) writeb_relaxed(pri, gic_dist_base(d) + GIC_DIST_PRI + gic_irq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void rmw_writeb(u8 bval, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static DEFINE_RAW_SPINLOCK(rmw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned long offset = (unsigned long)addr & 3UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned long shift = offset * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) raw_spin_lock_irqsave(&rmw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) addr -= offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val = readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val &= ~GENMASK(shift + 7, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) val |= bval << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) writel_relaxed(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) raw_spin_unlock_irqrestore(&rmw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) cpu = cpumask_any_and(mask_val, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) cpu = cpumask_first(mask_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (static_branch_unlikely(&needs_rmw_access))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rmw_writeb(gic_cpu_map[cpu], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) writeb_relaxed(gic_cpu_map[cpu], reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) irq_data_update_effective_affinity(d, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return IRQ_SET_MASK_OK_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned long flags, map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (unlikely(nr_cpu_ids == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* Only one CPU? let's do a self-IPI... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) writel_relaxed(2 << 24 | d->hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) gic_lock_irqsave(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /* Convert our logical CPU mask into a physical one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) for_each_cpu(cpu, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) map |= gic_cpu_map[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Ensure that stores to Normal memory are visible to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * other CPUs before they observe us issuing the IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dmb(ishst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* this always happens on GIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_FIQ_GLUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* enable non-secure SGI for GIC with security extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) writel_relaxed(map << 16 | d->hwirq | 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) gic_unlock_irqrestore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int gic_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) gic_cpu_init(&gic_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (IS_ENABLED(CONFIG_FIQ_GLUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* set SGI to none secure state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) writel_relaxed(0xffffffff, gic_data_dist_base(&gic_data[0]) + GIC_DIST_IGROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) writel_relaxed(0xf, gic_data_cpu_base(&gic_data[0]) + GIC_CPU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static __init void gic_smp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct irq_fwspec sgi_fwspec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .fwnode = gic_data[0].domain->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .param_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int base_sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "irqchip/arm/gic:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) gic_starting_cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) NUMA_NO_NODE, &sgi_fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (WARN_ON(base_sgi <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) set_smp_ipi_range(base_sgi, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define gic_smp_init() do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define gic_set_affinity NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define gic_ipi_send_mask NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #ifdef CONFIG_BL_SWITCHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * gic_send_sgi - send a SGI directly to given CPU interface number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * cpu_id: the ID for the destination CPU interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * irq: the IPI number to send a SGI for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) BUG_ON(cpu_id >= NR_GIC_CPU_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cpu_id = 1 << cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* this always happens on GIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * gic_get_cpu_id - get the CPU interface ID for the specified CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * @cpu: the logical CPU number to get the GIC ID for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Return the CPU interface ID for the given logical CPU number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * or -1 if the CPU number is too large or the interface ID is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * unknown (more than one bit set).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int gic_get_cpu_id(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) unsigned int cpu_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (cpu >= NR_GIC_CPU_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) cpu_bit = gic_cpu_map[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (cpu_bit & (cpu_bit - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return __ffs(cpu_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * gic_migrate_target - migrate IRQs to another CPU interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @new_cpu_id: the CPU target ID to migrate IRQs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Migrate all peripheral interrupts with a target matching the current CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * to the interface corresponding to @new_cpu_id. The CPU interface mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * is also updated. Targets to other CPU interfaces are unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * This must be called with IRQs locally disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void gic_migrate_target(unsigned int new_cpu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) void __iomem *dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int i, ror_val, cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u32 val, cur_target_mask, active_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dist_base = gic_data_dist_base(&gic_data[gic_nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) gic_irqs = gic_data[gic_nr].gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) cur_cpu_id = __ffs(gic_cpu_map[cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) cur_target_mask = 0x01010101 << cur_cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ror_val = (cur_cpu_id - new_cpu_id) & 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) gic_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Update the target interface for this logical CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) gic_cpu_map[cpu] = 1 << new_cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Find all the peripheral interrupts targeting the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * CPU interface and migrate them to the new CPU interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * We skip DIST_TARGET 0 to 7 as they are read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) active_mask = val & cur_target_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (active_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) val &= ~active_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) val |= ror32(active_mask, ror_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) gic_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * Now let's migrate and clear any potential SGIs that might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * is a banked register, we can only forward the SGI using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * doesn't use that information anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * For the same reason we do not adjust SGI source information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * for previously sent SGIs by us to other CPUs either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) for (i = 0; i < 16; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) for (j = i; j < i + 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (val & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) writel_relaxed((1 << (new_cpu_id + 16)) | j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dist_base + GIC_DIST_SOFTINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * gic_get_sgir_physaddr - get the physical address for the SGI register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * REturn the physical address of the SGI register to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * by some early assembly code when the kernel is not yet available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static unsigned long gic_dist_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned long gic_get_sgir_physaddr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!gic_dist_physaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return gic_dist_physaddr + GIC_DIST_SOFTINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void __init gic_init_physaddr(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (of_address_to_resource(node, 0, &res) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) gic_dist_physaddr = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define gic_init_physaddr(node) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct gic_chip_data *gic = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) switch (hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case 0 ... 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) handle_percpu_devid_fasteoi_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case 16 ... 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) handle_percpu_devid_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) handle_fasteoi_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) irqd_set_single_target(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* Prevents SW retriggers which mess up the ACK/EOI ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) irqd_set_handle_enforce_irqctx(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int gic_irq_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) *type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (fwspec->param_count < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) switch (fwspec->param[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case 0: /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) *hwirq = fwspec->param[1] + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case 1: /* PPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) *hwirq = fwspec->param[1] + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Make it clear that broken DTs are... broken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) WARN_ON(*type == IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (is_fwnode_irqchip(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if(fwspec->param_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) *type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) WARN_ON(*type == IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) unsigned int type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .translate = gic_irq_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .alloc = gic_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .free = irq_domain_free_irqs_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const struct irq_domain_ops gic_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .map = gic_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .unmap = gic_irq_domain_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) const char *name, bool use_eoimode1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* Initialize irq_chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) gic->chip = gic_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) gic->chip.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) gic->chip.parent_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (use_eoimode1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) gic->chip.irq_mask = gic_eoimode1_mask_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (gic == &gic_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) gic->chip.irq_set_affinity = gic_set_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) gic->chip.ipi_send_mask = gic_ipi_send_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int gic_init_bases(struct gic_chip_data *gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct fwnode_handle *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int gic_irqs, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Frankein-GIC without banked registers... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (WARN_ON(!gic->dist_base.percpu_base ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) !gic->cpu_base.percpu_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) u32 mpidr = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned long offset = gic->percpu_offset * core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) gic->raw_dist_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) gic->raw_cpu_base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) enable_frankengic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Normal, sane GIC... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) WARN(gic->percpu_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "GIC_NON_BANKED not enabled, ignoring %08x offset!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) gic->percpu_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) gic->dist_base.common_base = gic->raw_dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) gic->cpu_base.common_base = gic->raw_cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * Find out how many interrupts are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * The GIC only supports up to 1020 interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) gic_irqs = (gic_irqs + 1) * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (gic_irqs > 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) gic_irqs = 1020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) gic->gic_irqs = gic_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (handle) { /* DT/ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) gic->domain = irq_domain_create_linear(handle, gic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &gic_irq_domain_hierarchy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) } else { /* Legacy support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * For primary GICs, skip over SGIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * No secondary GIC support whatsoever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) gic_irqs -= 16; /* calculate # of irqs to allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) irq_base = irq_alloc_descs(16, 16, gic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) irq_base = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) 16, &gic_irq_domain_ops, gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (WARN_ON(!gic->domain)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) gic_dist_init(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = gic_cpu_init(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = gic_pm_init(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) free_percpu(gic->dist_base.percpu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) free_percpu(gic->cpu_base.percpu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static int __init __gic_init_bases(struct gic_chip_data *gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct fwnode_handle *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (WARN_ON(!gic || gic->domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (gic == &gic_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Initialize the CPU interface map to all CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * It will be refined as each CPU probes its ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * This is only necessary for the primary GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) for (i = 0; i < NR_GIC_CPU_IF; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) gic_cpu_map[i] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) set_handle_irq(gic_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (static_branch_likely(&supports_deactivate_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pr_info("GIC: Using split EOI/Deactivate mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) name = kasprintf(GFP_KERNEL, "GICv2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) gic_init_chip(gic, NULL, name, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) gic_init_chip(gic, NULL, name, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = gic_init_bases(gic, handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) else if (gic == &gic_data[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) gic_smp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct gic_chip_data *gic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * Non-DT/ACPI systems won't run a hypervisor, so let's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * bother with these...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static_branch_disable(&supports_deactivate_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) gic = &gic_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) gic->raw_dist_base = dist_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) gic->raw_cpu_base = cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __gic_init_bases(gic, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static void gic_teardown(struct gic_chip_data *gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (WARN_ON(!gic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (gic->raw_dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) iounmap(gic->raw_dist_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (gic->raw_cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) iounmap(gic->raw_cpu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static int gic_cnt __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static bool gicv2_force_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int __init gicv2_force_probe_cfg(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return strtobool(buf, &gicv2_force_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct resource cpuif_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) of_address_to_resource(node, 1, &cpuif_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!is_hyp_mode_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (resource_size(&cpuif_res) < SZ_8K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) void __iomem *alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * Check for a stupid firmware that only exposes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * first page of a GICv2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!gic_check_gicv2(*base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (!gicv2_force_probe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) alt = ioremap(cpuif_res.start, SZ_8K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (!gic_check_gicv2(alt + SZ_4K)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * The first page was that of a GICv2, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * the second was *something*. Let's trust it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * to be a GICv2, and update the mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) &cpuif_res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) iounmap(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) *base = alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * We detected *two* initial GICv2 pages in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * row. Could be a GICv2 aliased over two 64kB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * pages. Update the resource, map the iospace, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * pray.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) iounmap(alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) alt = ioremap(cpuif_res.start, SZ_128K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (!alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) &cpuif_res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) cpuif_res.end = cpuif_res.start + SZ_128K -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) iounmap(*base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) *base = alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (resource_size(&cpuif_res) == SZ_128K) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * Verify that we have the first 4kB of a GICv2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * aliased over the first 64kB by checking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * GICC_IIDR register on both ends.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!gic_check_gicv2(*base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) !gic_check_gicv2(*base + 0xf000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Move the base up by 60kB, so that we have a 8kB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * contiguous region, which allows us to use GICC_DIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * at its normal offset. Please pass me that bucket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) *base += 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) cpuif_res.start += 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pr_warn("GIC: Adjusting CPU interface base to %pa\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) &cpuif_res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static bool gic_enable_rmw_access(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * The EMEV2 class of machines has a broken interconnect, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * locks up on accesses that are less than 32bit. So far, only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * the affinity setting requires it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (of_machine_is_compatible("renesas,emev2")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static_branch_enable(&needs_rmw_access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const struct gic_quirk gic_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .desc = "broken byte access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .compatible = "arm,pl390",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .init = gic_enable_rmw_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!gic || !node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) gic->raw_dist_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) gic->raw_cpu_base = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) gic->percpu_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) gic_enable_of_quirks(node, gic_quirks, gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) gic_teardown(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (!dev || !dev->of_node || !gic || !irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (!*gic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) gic_init_chip(*gic, dev, dev->of_node->name, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ret = gic_of_setup(*gic, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = gic_init_bases(*gic, &dev->of_node->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) gic_teardown(*gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void __init gic_of_setup_kvm_info(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) gic_v2_kvm_info.type = GIC_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!gic_v2_kvm_info.maint_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = of_address_to_resource(node, 2, vctrl_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = of_address_to_resource(node, 3, vcpu_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (static_branch_likely(&supports_deactivate_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) gic_set_kvm_info(&gic_v2_kvm_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) gic_of_init(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct gic_chip_data *gic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (WARN_ON(!node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) gic = &gic_data[gic_cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ret = gic_of_setup(gic, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * Disable split EOI/Deactivate if either HYP is not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * or the CPU interface is too small.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static_branch_disable(&supports_deactivate_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = __gic_init_bases(gic, &node->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) gic_teardown(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!gic_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) gic_init_physaddr(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) gic_of_setup_kvm_info(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) gic_cascade_irq(gic_cnt, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) gic_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) phys_addr_t cpu_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) u32 maint_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) int maint_irq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) phys_addr_t vctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) phys_addr_t vcpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) } acpi_data __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) const unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct acpi_madt_generic_interrupt *processor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) phys_addr_t gic_cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int cpu_base_assigned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) processor = (struct acpi_madt_generic_interrupt *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (BAD_MADT_GICC_ENTRY(processor, end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * There is no support for non-banked GICv1/2 register in ACPI spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * All CPU interface addresses have to be the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) gic_cpu_base = processor->base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) acpi_data.cpu_phys_base = gic_cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) acpi_data.maint_irq = processor->vgic_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) acpi_data.vctrl_base = processor->gich_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) acpi_data.vcpu_base = processor->gicv_base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) cpu_base_assigned = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* The things you have to do to just *count* something... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static int __init acpi_dummy_func(union acpi_subtable_headers *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) const unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static bool __init acpi_gic_redist_is_present(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) acpi_dummy_func, 0) > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static bool __init gic_validate_dist(struct acpi_subtable_header *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct acpi_probe_entry *ape)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct acpi_madt_generic_distributor *dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dist = (struct acpi_madt_generic_distributor *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return (dist->version == ape->driver_data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) !acpi_gic_redist_is_present()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static void __init gic_acpi_setup_kvm_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) gic_v2_kvm_info.type = GIC_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (!acpi_data.vctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) vctrl_res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) vctrl_res->start = acpi_data.vctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (!acpi_data.vcpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) vcpu_res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) vcpu_res->start = acpi_data.vcpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) acpi_data.maint_irq_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ACPI_ACTIVE_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) gic_v2_kvm_info.maint_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) gic_set_kvm_info(&gic_v2_kvm_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) const unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct acpi_madt_generic_distributor *dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct fwnode_handle *domain_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct gic_chip_data *gic = &gic_data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) int count, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Collect CPU base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) gic_acpi_parse_madt_cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (count <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pr_err("No valid GICC entries exist\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!gic->raw_cpu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) pr_err("Unable to map GICC registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dist = (struct acpi_madt_generic_distributor *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) gic->raw_dist_base = ioremap(dist->base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ACPI_GICV2_DIST_MEM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (!gic->raw_dist_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) pr_err("Unable to map GICD registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) gic_teardown(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * Disable split EOI/Deactivate if HYP is not available. ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * guarantees that we'll always have a GICv2, so the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * interface will always be the right size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (!is_hyp_mode_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static_branch_disable(&supports_deactivate_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * Initialize GIC instance zero (no multi-GIC support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (!domain_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pr_err("Unable to allocate domain handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) gic_teardown(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ret = __gic_init_bases(gic, domain_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) pr_err("Failed to initialise GIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) irq_domain_free_fwnode(domain_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) gic_teardown(gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) gicv2m_init(NULL, gic_data[0].domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (static_branch_likely(&supports_deactivate_key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) gic_acpi_setup_kvm_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) gic_v2_acpi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) gic_v2_acpi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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