^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 ARM Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "GICv3: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip/arm-gic-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mbi_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 spi_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 nr_spis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned long *bm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static DEFINE_MUTEX(mbi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static phys_addr_t mbi_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct mbi_range *mbi_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static unsigned int mbi_range_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct irq_chip mbi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "MBI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct irq_data *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Using ACPI? There is no MBI support in the spec, you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * shouldn't even be here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!is_of_node(domain->parent->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Let's default to edge. This is consistent with traditional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * MSIs, and systems requiring level signaling will just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * enforce the trigger on their own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) fwspec.param[1] = hwirq - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) d = irq_domain_get_irq_data(domain->parent, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mutex_lock(&mbi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mutex_unlock(&mbi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) msi_alloc_info_t *info = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mbi_range *mbi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int hwirq, offset, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mutex_lock(&mbi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < mbi_range_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) offset = bitmap_find_free_region(mbi_ranges[i].bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mbi_ranges[i].nr_spis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mbi = &mbi_ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mutex_unlock(&mbi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!mbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) hwirq = mbi->spi_start + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) err = iommu_dma_prepare_msi(info->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mbi_phys_base + GICD_SETSPI_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &mbi_irq_chip, mbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mbi_free_msi(mbi, hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void mbi_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mbi_free_msi(mbi, d->hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct irq_domain_ops mbi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .alloc = mbi_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .free = mbi_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) msg[0].data = data->parent_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* PCI-specific irqchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void mbi_mask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void mbi_unmask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct irq_chip mbi_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .irq_mask = mbi_mask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .irq_unmask = mbi_unmask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .irq_compose_msi_msg = mbi_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .irq_write_msi_msg = pci_msi_domain_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct msi_domain_info mbi_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .chip = &mbi_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct irq_domain **pci_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *pci_domain = pci_msi_create_irq_domain(nexus_domain->parent->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &mbi_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) nexus_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!*pci_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct irq_domain **pci_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *pci_domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mbi_compose_msi_msg(data, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) msg[1].data = data->parent_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Platform-MSI specific irqchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct irq_chip mbi_pmsi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "pMSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .irq_compose_msi_msg = mbi_compose_mbi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .flags = IRQCHIP_SUPPORTS_LEVEL_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct msi_domain_ops mbi_pmsi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct msi_domain_info mbi_pmsi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MSI_FLAG_LEVEL_CAPABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .ops = &mbi_pmsi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .chip = &mbi_pmsi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int mbi_allocate_domains(struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct irq_domain *nexus_domain, *pci_domain, *plat_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) nexus_domain = irq_domain_create_tree(parent->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &mbi_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!nexus_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) nexus_domain->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = mbi_allocate_pci_domain(nexus_domain, &pci_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) plat_domain = platform_msi_create_irq_domain(parent->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &mbi_pmsi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) nexus_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (err || !plat_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (plat_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq_domain_remove(plat_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (pci_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq_domain_remove(pci_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) irq_domain_remove(nexus_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const __be32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) np = to_of_node(fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!of_property_read_bool(np, "msi-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (n <= 0 || n % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mbi_range_nr = n / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mbi_ranges = kcalloc(mbi_range_nr, sizeof(*mbi_ranges), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!mbi_ranges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (n = 0; n < mbi_range_nr; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &mbi_ranges[n].spi_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) &mbi_ranges[n].nr_spis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mbi_ranges[n].bm = kcalloc(BITS_TO_LONGS(mbi_ranges[n].nr_spis),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sizeof(long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!mbi_ranges[n].bm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = of_get_property(np, "mbi-alias", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mbi_phys_base = of_translate_address(np, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (of_address_to_resource(np, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mbi_phys_base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pr_info("Using MBI frame %pa\n", &mbi_phys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = mbi_allocate_domains(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto err_free_mbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) err_free_mbi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (mbi_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (n = 0; n < mbi_range_nr; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) kfree(mbi_ranges[n].bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) kfree(mbi_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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