Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/acpi_iort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static void its_mask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static void its_unmask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct irq_chip its_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.name			= "ITS-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.irq_unmask		= its_unmask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.irq_mask		= its_mask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.irq_write_msi_msg	= pci_msi_domain_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int msi, msix, *count = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	msi = max(pci_msi_vec_count(pdev), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	msix = max(pci_msix_vec_count(pdev), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	*count += max(msi, msix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct pci_dev **alias_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	*alias_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			       int nvec, msi_alloc_info_t *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct pci_dev *pdev, *alias_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct msi_domain_info *msi_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int alias_count = 0, minnvec = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (!dev_is_pci(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	msi_info = msi_get_domain_info(domain->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * If pdev is downstream of any aliasing bridges, take an upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * bound of how many other vectors could map to the same DevID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (alias_dev != pdev && alias_dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			     &alias_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* ITS specific DeviceID, as the core ITS ignores dev. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * Always allocate a power of 2, and special case device 0 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * broken systems where the DevID is not wired (and all devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * appear as DevID 0). For that reason, we generously allocate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * minimum of 32 MSIs for DevID 0. If you want more because all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * your devices are aliasing to DevID 0, consider fixing your HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	nvec = max(nvec, alias_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (!info->scratchpad[0].ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		minnvec = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	nvec = max_t(int, minnvec, roundup_pow_of_two(nvec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct msi_domain_ops its_pci_msi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.msi_prepare	= its_pci_msi_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static struct msi_domain_info its_pci_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		   MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.ops	= &its_pci_msi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.chip	= &its_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct of_device_id its_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{	.compatible	= "arm,gic-v3-its",	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int __init its_pci_msi_init_one(struct fwnode_handle *handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				       const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct irq_domain *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	parent = irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (!parent || !msi_get_domain_info(parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		pr_err("%s: Unable to locate ITS domain\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (!pci_msi_create_irq_domain(handle, &its_pci_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				       parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		pr_err("%s: Unable to create PCI domain\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int __init its_pci_of_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	for (np = of_find_matching_node(NULL, its_device_id); np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	     np = of_find_matching_node(np, its_device_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (!of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (!of_property_read_bool(np, "msi-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if (its_pci_msi_init_one(of_node_to_fwnode(np), np->full_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		pr_info("PCI/MSI: %pOF domain created\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) its_pci_msi_parse_madt(union acpi_subtable_headers *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		       const unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct acpi_madt_generic_translator *its_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct fwnode_handle *dom_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	const char *node_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	its_entry = (struct acpi_madt_generic_translator *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			      (long)its_entry->base_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dom_handle = iort_find_domain_token(its_entry->translation_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!dom_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		pr_err("%s: Unable to locate ITS domain handle\n", node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	err = its_pci_msi_init_one(dom_handle, node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		pr_info("PCI/MSI: %s domain created\n", node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	kfree(node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int __init its_pci_acpi_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			      its_pci_msi_parse_madt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int __init its_pci_acpi_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int __init its_pci_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	its_pci_of_msi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	its_pci_acpi_msi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) early_initcall(its_pci_msi_init);