^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARM GIC v2m MSI(-X) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Support for Message Signaled Interrupts for systems that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * implement ARM Generic Interrupt Controller: GICv2m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2014 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Brandon Anderson <brandon.anderson@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) "GICv2m: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * MSI_TYPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * [31:26] Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * [25:16] lowest SPI assigned to MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * [15:10] Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * [9:0] Numer of SPIs assigned to MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V2M_MSI_TYPER 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V2M_MSI_TYPER_BASE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define V2M_MSI_TYPER_BASE_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V2M_MSI_TYPER_NUM_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V2M_MSI_SETSPI_NS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V2M_MIN_SPI 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define V2M_MAX_SPI 1019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define V2M_MSI_IIDR 0xFCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define V2M_MSI_TYPER_BASE_SPI(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* APM X-Gene with GICv2m MSI_IIDR register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XGENE_GICV2M_MSI_IIDR 0x06000170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Broadcom NS2 GICv2m MSI_IIDR register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* List of flags for specific v2m implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GICV2M_NEEDS_SPI_OFFSET 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static LIST_HEAD(v2m_nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static DEFINE_SPINLOCK(v2m_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct v2m_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct resource res; /* GICv2m resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *base; /* GICv2m virt address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 spi_start; /* The SPI number that MSIs start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 nr_spis; /* The number of SPIs for MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 spi_offset; /* offset to be subtracted from SPI number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long *bm; /* MSI vector bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 flags; /* v2m flags for specific implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void gicv2m_mask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void gicv2m_unmask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct irq_chip gicv2m_msi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .irq_mask = gicv2m_mask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .irq_unmask = gicv2m_unmask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .irq_write_msi_msg = pci_msi_domain_write_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct msi_domain_info gicv2m_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .chip = &gicv2m_msi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return v2m->res.start | ((hwirq - 32) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return v2m->res.start + V2M_MSI_SETSPI_NS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) msg->address_hi = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) msg->address_lo = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) msg->data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) msg->data = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) msg->data -= v2m->spi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct irq_chip gicv2m_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "GICv2m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .irq_eoi = irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .irq_set_affinity = irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .irq_compose_msi_msg = gicv2m_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct irq_data *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (is_of_node(domain->parent->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fwspec.param[1] = hwirq - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fwspec.param[0] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Configure the interrupt line to be edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) d = irq_domain_get_irq_data(domain->parent, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spin_lock(&v2m_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spin_unlock(&v2m_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) msi_alloc_info_t *info = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct v2m_data *v2m = NULL, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int hwirq, offset, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_lock(&v2m_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) list_for_each_entry(tmp, &v2m_nodes, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) get_count_order(nr_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) v2m = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_unlock(&v2m_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!v2m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) hwirq = v2m->spi_start + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = iommu_dma_prepare_msi(info->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gicv2m_get_msi_addr(v2m, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) &gicv2m_irq_chip, v2m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void gicv2m_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct irq_domain_ops gicv2m_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .alloc = gicv2m_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .free = gicv2m_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static bool is_msi_spi_valid(u32 base, u32 num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (base < V2M_MIN_SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_err("Invalid MSI base SPI (base:%u)\n", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if ((num == 0) || (base + num > V2M_MAX_SPI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct irq_chip gicv2m_pmsi_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "pMSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct msi_domain_ops gicv2m_pmsi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct msi_domain_info gicv2m_pmsi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ops = &gicv2m_pmsi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .chip = &gicv2m_pmsi_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void gicv2m_teardown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct v2m_data *v2m, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) list_del(&v2m->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) kfree(v2m->bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) iounmap(v2m->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) of_node_put(to_of_node(v2m->fwnode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (is_fwnode_irqchip(v2m->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) irq_domain_free_fwnode(v2m->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) kfree(v2m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int gicv2m_allocate_domains(struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct irq_domain *inner_domain, *pci_domain, *plat_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct v2m_data *v2m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!v2m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) inner_domain = irq_domain_create_tree(v2m->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &gicv2m_domain_ops, v2m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!inner_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pr_err("Failed to create GICv2m domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) inner_domain->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &gicv2m_msi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) &gicv2m_pmsi_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!pci_domain || !plat_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pr_err("Failed to create MSI domains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (plat_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) irq_domain_remove(plat_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (pci_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) irq_domain_remove(pci_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) irq_domain_remove(inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 spi_start, u32 nr_spis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct resource *res, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct v2m_data *v2m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!v2m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pr_err("Failed to allocate struct v2m_data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) INIT_LIST_HEAD(&v2m->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) v2m->fwnode = fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) v2m->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) memcpy(&v2m->res, res, sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!v2m->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_err("Failed to map GICv2m resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto err_free_v2m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (spi_start && nr_spis) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) v2m->spi_start = spi_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) v2m->nr_spis = nr_spis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 typer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Graviton should always have explicit spi_start/nr_spis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * APM X-Gene GICv2m implementation has an erratum where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * the MSI data needs to be the offset from the spi_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * in order to trigger the correct MSI interrupt. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * different from the standard GICv2m implementation where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * the MSI data is the absolute value within the range from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * spi_start to (spi_start + num_spis).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Broadom NS2 GICv2m implementation has an erratum where the MSI data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * is 'spi_number - 32'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Reading that register fails on the Graviton implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case XGENE_GICV2M_MSI_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) v2m->spi_offset = v2m->spi_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case BCM_NS2_GICV2M_MSI_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) v2m->spi_offset = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) v2m->bm = kcalloc(BITS_TO_LONGS(v2m->nr_spis), sizeof(long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!v2m->bm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) list_add_tail(&v2m->entry, &v2m_nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pr_info("range%pR, SPI[%d:%d]\n", res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) iounmap(v2m->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err_free_v2m:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) kfree(v2m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct of_device_id gicv2m_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { .compatible = "arm,gic-v2m-frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct device_node *node = to_of_node(parent_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (child = of_find_matching_node(node, gicv2m_device_id); child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) child = of_find_matching_node(child, gicv2m_device_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 spi_start = 0, nr_spis = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!of_find_property(child, "msi-controller", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = of_address_to_resource(child, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pr_err("Failed to allocate v2m resource.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!of_property_read_u32(child, "arm,msi-base-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &spi_start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) spi_start, nr_spis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &res, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = gicv2m_allocate_domains(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) gicv2m_teardown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int acpi_num_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct v2m_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (WARN_ON(acpi_num_msi <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* We only return the fwnode of the first MSI frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return data->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static bool acpi_check_amazon_graviton_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct acpi_table_madt *madt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) bool rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define ACPI_AMZN_OEM_ID "AMAZON"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) status = acpi_get_table(ACPI_SIG_MADT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (struct acpi_table_header **)&madt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ACPI_FAILURE(status) || !madt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) acpi_put_table((struct acpi_table_header *)madt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) acpi_parse_madt_msi(union acpi_subtable_headers *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) const unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 spi_start = 0, nr_spis = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct acpi_madt_generic_msi_frame *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) m = (struct acpi_madt_generic_msi_frame *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (BAD_MADT_ENTRY(m, end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) res.start = m->base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) res.end = m->base_address + SZ_4K - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (acpi_check_amazon_graviton_quirks()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pr_info("applying Amazon Graviton quirk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) res.end = res.start + SZ_8K - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spi_start = m->spi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) nr_spis = m->spi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spi_start, nr_spis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) fwnode = irq_domain_alloc_fwnode(&res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pr_err("Unable to allocate GICv2m domain token\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) irq_domain_free_fwnode(fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int __init gicv2m_acpi_init(struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (acpi_num_msi > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) acpi_parse_madt_msi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (acpi_num_msi <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = gicv2m_allocate_domains(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) gicv2m_teardown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #else /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int __init gicv2m_acpi_init(struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int __init gicv2m_init(struct fwnode_handle *parent_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct irq_domain *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (is_of_node(parent_handle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return gicv2m_of_init(parent_handle, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return gicv2m_acpi_init(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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