Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Special GIC quirks for the ARM RealView
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2015 Linus Walleij
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REALVIEW_SYS_LOCK_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define REALVIEW_SYS_PLD_CTRL1		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REALVIEW_EB_REVB_SYS_PLD_CTRL1	0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VERSATILE_LOCK_VAL		0xA05F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLD_INTMODE_MASK		BIT(22)|BIT(23)|BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PLD_INTMODE_LEGACY		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLD_INTMODE_NEW_DCC		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PLD_INTMODE_NEW_NO_DCC		BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLD_INTMODE_FIQ_ENABLE		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* For some reason RealView EB Rev B moved this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct of_device_id syscon_pldset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.compatible = "arm,realview-eb11mp-revb-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		.compatible = "arm,realview-eb11mp-revc-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		.data = (void *)REALVIEW_SYS_PLD_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		.compatible = "arm,realview-eb-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		.data = (void *)REALVIEW_SYS_PLD_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		.compatible = "arm,realview-pb11mp-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		.data = (void *)REALVIEW_SYS_PLD_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) realview_gic_of_init(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	const struct of_device_id *gic_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u32 pld1_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 					     &gic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	pld1_ctrl = (u32)gic_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	/* The PB11MPCore GIC needs to be configured in the syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	map = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (!IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		/* new irq mode with no DCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			     VERSATILE_LOCK_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		regmap_update_bits(map, pld1_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 				   PLD_INTMODE_NEW_NO_DCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 				   PLD_INTMODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		pr_err("RealView GIC setup: could not find syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	return gic_of_init(node, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);