^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 ARM Limited, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "irq-gic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static DEFINE_RAW_SPINLOCK(irq_controller_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct gic_kvm_info *gic_kvm_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) const struct gic_kvm_info *gic_get_kvm_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) return gic_kvm_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void gic_set_kvm_info(const struct gic_kvm_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) BUG_ON(gic_kvm_info != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) gic_kvm_info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void gic_enable_of_quirks(const struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const struct gic_quirk *quirks, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) for (; quirks->desc; quirks++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (!of_device_is_compatible(np, quirks->compatible))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (quirks->init(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pr_info("GIC: enabling workaround for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) quirks->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for (; quirks->desc; quirks++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (quirks->compatible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (quirks->iidr != (quirks->mask & iidr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (quirks->init(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pr_info("GIC: enabling workaround for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) quirks->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int gic_configure_irq(unsigned int irq, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *base, void (*sync_access)(void))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 confmask = 0x2 << ((irq % 16) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 confoff = (irq / 16) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 val, oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Read current configuration register, and insert the config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * for "irq", depending on "type".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) raw_spin_lock_irqsave(&irq_controller_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val = oldval = readl_relaxed(base + confoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val &= ~confmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) else if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val |= confmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* If the current configuration is the same, then we are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (val == oldval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Write back the new configuration, and possibly re-enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the interrupt. If we fail to write a new configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * an SPI then WARN and return an error. If we fail to write the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * configuration for a PPI this is most likely because the GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * does not allow us to set the configuration or we are in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * non-secure mode, and hence it may not be catastrophic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel_relaxed(val, base + confoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (readl_relaxed(base + confoff) != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (sync_access)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sync_access();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void gic_dist_config(void __iomem *base, int gic_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void (*sync_access)(void))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Set all global interrupts to be level triggered, active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) for (i = 32; i < gic_irqs; i += 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) base + GIC_DIST_CONFIG + i / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Set priority on all global interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 32; i < gic_irqs; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Deactivate and disable all SPIs. Leave the PPI and SGIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * alone as they are in the redistributor registers on GICv3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 32; i < gic_irqs; i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) base + GIC_DIST_ACTIVE_CLEAR + i / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) base + GIC_DIST_ENABLE_CLEAR + i / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (sync_access)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sync_access();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Deal with the banked PPI and SGI interrupts - disable all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * private interrupts. Make sure everything is deactivated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (i = 0; i < nr; i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) base + GIC_DIST_ACTIVE_CLEAR + i / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel_relaxed(GICD_INT_EN_CLR_X32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) base + GIC_DIST_ENABLE_CLEAR + i / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Set priority on PPI and SGI interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < nr; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel_relaxed(GICD_INT_DEF_PRI_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) base + GIC_DIST_PRI + i * 4 / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (sync_access)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sync_access();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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