^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * irqchip for the Faraday Technology FTINTC010 Copyright (C) 2017 Linus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on arch/arm/mach-gemini/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001-2006 Storlink, Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip/versatile-fpga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FT010_NUM_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Selects level- or edge-triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Selects active low/high or falling/rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FT010_FIQ_POLARITY(base_addr) (base_addr + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FT010_FIQ_STATUS(base_addr) (base_addr + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * struct ft010_irq_data - irq data container for the Faraday IRQ controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @base: memory offset in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @chip: chip container for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @domain: IRQ domain for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct ft010_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void ft010_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mask = readl(FT010_IRQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mask &= ~BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel(mask, FT010_IRQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void ft010_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mask = readl(FT010_IRQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mask |= BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(mask, FT010_IRQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void ft010_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct ft010_irq_data *f = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 mode, polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mode = readl(FT010_IRQ_MODE(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) polarity = readl(FT010_IRQ_POLARITY(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (trigger & (IRQ_TYPE_LEVEL_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mode &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) polarity |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } else if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mode &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) polarity &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mode |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) polarity |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } else if (trigger & IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mode |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) polarity &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) irq_set_handler_locked(d, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pr_warn("Faraday IRQ: no supported trigger selected for line %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(mode, FT010_IRQ_MODE(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(polarity, FT010_IRQ_POLARITY(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct irq_chip ft010_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "FTINTC010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .irq_ack = ft010_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .irq_mask = ft010_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .irq_unmask = ft010_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .irq_set_type = ft010_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Local static for the IRQ entry call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct ft010_irq_data firq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) asmlinkage void __exception_irq_entry ft010_irqchip_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ft010_irq_data *f = &firq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) while ((status = readl(FT010_IRQ_STATUS(f->base)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) irq = ffs(status) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) handle_domain_irq(f->domain, irq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ft010_irqdomain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ft010_irq_data *f = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq_set_chip_data(irq, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* All IRQs should set up their type, flags as bad by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_set_chip_and_handler(irq, &ft010_irq_chip, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void ft010_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irq_set_chip_and_handler(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct irq_domain_ops ft010_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .map = ft010_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .unmap = ft010_irqdomain_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int __init ft010_of_init_irq(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ft010_irq_data *f = &firq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Disable the idle handler by default since it is buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * For more info see arch/arm/mach-gemini/idle.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpu_idle_poll_ctrl(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) f->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) WARN(!f->base, "unable to map gemini irq registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(0, FT010_IRQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(0, FT010_FIQ_MASK(f->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) f->domain = irq_domain_add_simple(node, FT010_NUM_IRQS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &ft010_irqdomain_ops, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) set_handle_irq(ft010_irqchip_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IRQCHIP_DECLARE(faraday, "faraday,ftintc010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ft010_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ft010_of_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IRQCHIP_DECLARE(moxa, "moxa,moxart-ic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ft010_of_init_irq);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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