Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Synopsys DW APB ICTL irqchip driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * based on GPL'ed 2.6 kernel sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  (c) Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define APB_INT_ENABLE_L	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define APB_INT_ENABLE_H	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define APB_INT_MASK_L		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define APB_INT_MASK_H		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define APB_INT_FINALSTATUS_L	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define APB_INT_FINALSTATUS_H	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define APB_INT_BASE_OFFSET	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* irq domain of the primary interrupt controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static struct irq_domain *dw_apb_ictl_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct irq_domain *d = dw_apb_ictl_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	for (n = 0; n < d->revmap_size; n += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			u32 hwirq = ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			handle_domain_irq(d, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			stat &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct irq_domain *d = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	for (n = 0; n < d->revmap_size; n += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			u32 hwirq = ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			stat &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned int type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct irq_fwspec *fwspec = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		irq_map_generic_chip(domain, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.translate = irq_domain_translate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.alloc = dw_apb_ictl_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.free = irq_domain_free_irqs_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void dw_apb_ictl_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writel_relaxed(~0, gc->reg_base + ct->regs.enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define dw_apb_ictl_resume	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int __init dw_apb_ictl_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				   struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	const struct irq_domain_ops *domain_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret, nrirqs, parent_irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/* Used as the primary interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		parent_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		domain_ops = &dw_apb_ictl_irq_domain_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/* Map the parent interrupt for the chained handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		parent_irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (parent_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			pr_err("%pOF: unable to parse irq\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		domain_ops = &irq_generic_chip_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = of_address_to_resource(np, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		pr_err("%pOF: unable to get resource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		pr_err("%pOF: unable to request mem region\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	iobase = ioremap(r.start, resource_size(&r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		pr_err("%pOF: unable to map resource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * DW IP can be configured to allow 2-64 irqs. We can determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * the number of irqs supported by writing into enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 * and look for bits not set, as corresponding flip-flops will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * have been removed by synthesis tool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* mask and enable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	writel_relaxed(~0, iobase + APB_INT_MASK_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	writel_relaxed(~0, iobase + APB_INT_MASK_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	writel_relaxed(~0, iobase + APB_INT_ENABLE_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	writel_relaxed(~0, iobase + APB_INT_ENABLE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	reg = readl_relaxed(iobase + APB_INT_ENABLE_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		nrirqs = 32 + fls(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		pr_err("%pOF: unable to add irq domain\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					     handle_level_irq, clr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					     IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		pr_err("%pOF: unable to alloc irq domain gc\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		gc = irq_get_domain_generic_chip(domain, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		gc->reg_base = iobase + i * APB_INT_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		gc->chip_types[0].regs.mask = APB_INT_MASK_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				dw_apb_ictl_handle_irq_cascaded, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dw_apb_ictl_irq_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		set_handle_irq(dw_apb_ictl_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	iounmap(iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	release_mem_region(r.start, resource_size(&r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IRQCHIP_DECLARE(dw_apb_ictl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		"snps,dw-apb-ictl", dw_apb_ictl_init);