Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Author: Steve Chen <schen@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright (C) 2019, Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // TI Common Platform Interrupt Controller (cp_intc) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqchip/irq-davinci-cp-intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DAVINCI_CP_INTC_CTRL			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DAVINCI_CP_INTC_HOST_CTRL		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DAVINCI_CP_INTC_GLOBAL_ENABLE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DAVINCI_CP_INTC_PRIO_IDX		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DAVINCI_CP_INTC_SYS_STAT_CLR(n)		(0x0280 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n)	(0x0380 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DAVINCI_CP_INTC_CHAN_MAP(n)		(0x0400 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DAVINCI_CP_INTC_SYS_POLARITY(n)		(0x0d00 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DAVINCI_CP_INTC_SYS_TYPE(n)		(0x0d80 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DAVINCI_CP_INTC_HOST_ENABLE(n)		(0x1500 + (n << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DAVINCI_CP_INTC_PRI_INDX_MASK		GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DAVINCI_CP_INTC_GPIR_NONE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static void __iomem *davinci_cp_intc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static struct irq_domain *davinci_cp_intc_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline unsigned int davinci_cp_intc_read(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return readl_relaxed(davinci_cp_intc_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline void davinci_cp_intc_write(unsigned long value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					 unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	writel_relaxed(value, davinci_cp_intc_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void davinci_cp_intc_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void davinci_cp_intc_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/* XXX don't know why we need to disable nIRQ here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void davinci_cp_intc_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int davinci_cp_intc_set_irq_type(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned int reg, mask, polarity, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	reg = BIT_WORD(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	mask = BIT_MASK(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		polarity &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		type &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		polarity &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		type &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct irq_chip davinci_cp_intc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.name		= "cp_intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.irq_ack	= davinci_cp_intc_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.irq_mask	= davinci_cp_intc_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.irq_unmask	= davinci_cp_intc_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.irq_set_type	= davinci_cp_intc_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.flags		= IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static asmlinkage void __exception_irq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) davinci_cp_intc_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int gpir, irqnr, none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * The interrupt number is in first ten bits. The NONE field set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * indicates a spurious irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (unlikely(none)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		pr_err_once("%s: spurious irq!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			  irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	irq_set_chip(virq, &davinci_cp_intc_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	irq_set_probe(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	irq_set_handler(virq, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.map = davinci_cp_intc_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int offset, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	void __iomem *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	req = request_mem_region(config->reg.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				 resource_size(&config->reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				 "davinci-cp-intc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		pr_err("%s: register range busy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	davinci_cp_intc_base = ioremap(config->reg.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				       resource_size(&config->reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!davinci_cp_intc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		pr_err("%s: unable to ioremap register range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Disable all host interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Disable system interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (offset = 0; offset < num_regs; offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		davinci_cp_intc_write(~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Set to normal mode, no nesting, no priority hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* Clear system interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	for (offset = 0; offset < num_regs; offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		davinci_cp_intc_write(~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Enable nIRQ (what about nFIQ?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Default all priorities to channel 7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	num_regs = (config->num_irqs + 3) >> 2;	/* 4 channels per register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	for (offset = 0; offset < num_regs; offset++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		davinci_cp_intc_write(0x07070707,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			DAVINCI_CP_INTC_CHAN_MAP(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		pr_err("%s: unable to allocate interrupt descriptors: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		       __func__, irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	davinci_cp_intc_irq_domain = irq_domain_add_legacy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 					node, config->num_irqs, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					&davinci_cp_intc_irq_domain_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!davinci_cp_intc_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		pr_err("%s: unable to create an interrupt domain\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	set_handle_irq(davinci_cp_intc_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* Enable global interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return davinci_cp_intc_do_init(config, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int __init davinci_cp_intc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					  struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct davinci_cp_intc_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = of_address_to_resource(node, 0, &config.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		pr_err("%s: unable to get the register range from device-tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		       __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		pr_err("%s: unable to read the 'ti,intc-size' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		       __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return davinci_cp_intc_do_init(&config, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);