^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/reg_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct irq_domain *root_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void __iomem *INTCG_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void __iomem *INTCL_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IPI_IRQ 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTC_IRQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define COMM_IRQ_BASE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTCG_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INTCL_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define INTCG_ICTLR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define INTCG_CICFGR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define INTCG_CIDSTR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define INTCL_PICTLR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INTCL_CFGR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define INTCL_SIGR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define INTCL_RDYIR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INTCL_SENR 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define INTCL_CENR 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define INTCL_CACR 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static DEFINE_PER_CPU(void __iomem *, intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned long *__trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IRQ_OFFSET(irq) ((irq < COMM_IRQ_BASE) ? irq : (irq - COMM_IRQ_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TRIG_BYTE_OFFSET(i) ((((i) * 2) / 32) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TRIG_BIT_OFFSET(i) (((i) * 2) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TRIG_VAL(trigger, irq) (trigger << TRIG_BIT_OFFSET(IRQ_OFFSET(irq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TRIG_VAL_MSK(irq) (~(3 << TRIG_BIT_OFFSET(IRQ_OFFSET(irq))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TRIG_BASE(irq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (TRIG_BYTE_OFFSET(IRQ_OFFSET(irq)) + ((irq < COMM_IRQ_BASE) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (this_cpu_read(intcl_reg) + INTCL_CFGR) : (INTCG_base + INTCG_CICFGR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static DEFINE_SPINLOCK(setup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void setup_trigger(unsigned long irq, unsigned long trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spin_lock(&setup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* setup trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tmp = readl_relaxed(TRIG_BASE(irq)) & TRIG_VAL_MSK(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel_relaxed(tmp | TRIG_VAL(trigger, irq), TRIG_BASE(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_unlock(&setup_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void csky_mpintc_handler(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __iomem *reg_base = this_cpu_read(intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) handle_domain_irq(root_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) readl_relaxed(reg_base + INTCL_RDYIR), regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void csky_mpintc_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *reg_base = this_cpu_read(intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) setup_trigger(d->hwirq, __trigger[d->hwirq]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void csky_mpintc_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *reg_base = this_cpu_read(intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void csky_mpintc_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *reg_base = this_cpu_read(intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int csky_mpintc_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __trigger[d->hwirq] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __trigger[d->hwirq] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __trigger[d->hwirq] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __trigger[d->hwirq] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int csky_irq_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct cpumask *mask_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cpu = cpumask_any_and(mask_val, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) cpu = cpumask_first(mask_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (cpu >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * The csky,mpintc could support auto irq deliver, but it only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * could deliver external irq to one cpu or all cpus. So it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * doesn't support deliver external irq to a group of cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * with cpu_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * SO we only use auto deliver mode when affinity mask_val is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * equal to cpu_present_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (cpumask_equal(mask_val, cpu_present_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cpu |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) irq_data_update_effective_affinity(d, cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return IRQ_SET_MASK_OK_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct irq_chip csky_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "C-SKY SMP Intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .irq_eoi = csky_mpintc_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .irq_enable = csky_mpintc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .irq_disable = csky_mpintc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .irq_set_type = csky_mpintc_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .irq_set_affinity = csky_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (hwirq < COMM_IRQ_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irq_set_chip_and_handler(irq, &csky_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irq_set_chip_and_handler(irq, &csky_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int csky_irq_domain_xlate_cells(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct device_node *ctrlr, const u32 *intspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int intsize, unsigned long *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (WARN_ON(intsize < 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (intsize > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *out_type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct irq_domain_ops csky_irqdomain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .map = csky_irqdomain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .xlate = csky_irq_domain_xlate_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void csky_mpintc_send_ipi(const struct cpumask *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __iomem *reg_base = this_cpu_read(intcl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * INTCL_SIGR[3:0] INTID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * INTCL_SIGR[8:15] CPUMASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg_base + INTCL_SIGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* C-SKY multi processor interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) csky_mpintc_init(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int cpu, nr_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int ipi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) nr_irq = INTC_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __trigger = kcalloc(nr_irq, sizeof(unsigned long), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (__trigger == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (INTCG_base == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) INTCG_base = ioremap(mfcr("cr<31, 14>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (INTCG_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) INTCL_base = INTCG_base + INTCG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!root_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* for every cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for_each_present_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) set_handle_irq(&csky_mpintc_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!ipi_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) set_send_ipi(&csky_mpintc_send_ipi, ipi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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