Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  drivers/irqchip/irq-crossbar.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Author: Sricharan R <r.sricharan@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IRQ_FREE	-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IRQ_RESERVED	-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IRQ_SKIP	-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define GIC_IRQ_START	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * struct crossbar_device - crossbar device description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @lock: spinlock serializing access to @irq_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * @int_max: maximum number of supported interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * @safe_map: safe default value to initialize the crossbar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * @max_crossbar_sources: Maximum number of crossbar sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @irq_map: array of interrupts to crossbar number mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * @crossbar_base: crossbar base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @register_offsets: offsets for each irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @write: register write function pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct crossbar_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	uint int_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	uint safe_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	uint max_crossbar_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	uint *irq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem *crossbar_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int *register_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	void (*write)(int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct crossbar_device *cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void crossbar_writel(int irq_no, int cb_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void crossbar_writew(int irq_no, int cb_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void crossbar_writeb(int irq_no, int cb_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct irq_chip crossbar_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.name			= "CBAR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.irq_set_type		= irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.flags			= IRQCHIP_MASK_ON_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				  IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			    irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (!irq_domain_get_of_node(domain->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	raw_spin_lock(&cb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	for (i = cb->int_max - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		if (cb->irq_map[i] == IRQ_FREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			cb->irq_map[i] = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	raw_spin_unlock(&cb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	fwspec.param[0] = 0;	/* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	fwspec.param[1] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		cb->irq_map[i] = IRQ_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		cb->write(i, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				 unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -EINVAL;	/* Not GIC compliant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EINVAL;	/* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;	/* Can't deal with this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		int err = allocate_gic_irq(d, virq + i, hwirq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 					      &crossbar_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * crossbar_domain_free - unmap/free a crossbar<->irq connection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * @domain: domain of irq to unmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * @virq: virq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * @nr_irqs: number of irqs to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * We do not maintain a use count of total number of map/unmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * calls for a particular irq to find out if a irq can be really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * after which irq is anyways unusable. So an explicit map has to be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * after that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	raw_spin_lock(&cb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		irq_domain_reset_irq_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		cb->irq_map[d->hwirq] = IRQ_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		cb->write(d->hwirq, cb->safe_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	raw_spin_unlock(&cb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int crossbar_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				     struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				     unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				     unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (is_of_node(fwspec->fwnode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (fwspec->param_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/* No PPI should point to this domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (fwspec->param[0] != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		*hwirq = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct irq_domain_ops crossbar_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.alloc		= crossbar_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.free		= crossbar_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.translate	= crossbar_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int __init crossbar_of_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 max = 0, entry, reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int i, size, reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	const __be32 *irqsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	cb = kzalloc(sizeof(*cb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (!cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	cb->crossbar_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!cb->crossbar_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		goto err_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	of_property_read_u32(node, "ti,max-crossbar-sources",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			     &cb->max_crossbar_sources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!cb->max_crossbar_sources) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		pr_err("missing 'ti,max-crossbar-sources' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		goto err_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	of_property_read_u32(node, "ti,max-irqs", &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		pr_err("missing 'ti,max-irqs' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		goto err_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!cb->irq_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	cb->int_max = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	for (i = 0; i < max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		cb->irq_map[i] = IRQ_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Get and mark reserved irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	irqsr = of_get_property(node, "ti,irqs-reserved", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (irqsr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		size /= sizeof(__be32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			of_property_read_u32_index(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 						   "ti,irqs-reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 						   i, &entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			if (entry >= max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				pr_err("Invalid reserved entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				goto err_irq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			cb->irq_map[entry] = IRQ_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Skip irqs hardwired to bypass the crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	irqsr = of_get_property(node, "ti,irqs-skip", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (irqsr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		size /= sizeof(__be32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			of_property_read_u32_index(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 						   "ti,irqs-skip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 						   i, &entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			if (entry >= max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				pr_err("Invalid skip entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				goto err_irq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			cb->irq_map[entry] = IRQ_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!cb->register_offsets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		goto err_irq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	of_property_read_u32(node, "ti,reg-size", &reg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	switch (reg_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		cb->write = crossbar_writeb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		cb->write = crossbar_writew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		cb->write = crossbar_writel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		pr_err("Invalid reg-size property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		goto err_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * Register offsets are not linear because of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * reserved irqs. so find and store the offsets once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	for (i = 0; i < max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		if (cb->irq_map[i] == IRQ_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		cb->register_offsets[i] = reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		reserved += reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* Initialize the crossbar with safe map to start with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	for (i = 0; i < max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (cb->irq_map[i] == IRQ_RESERVED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		    cb->irq_map[i] == IRQ_SKIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		cb->write(i, cb->safe_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	raw_spin_lock_init(&cb->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) err_reg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	kfree(cb->register_offsets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err_irq_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	kfree(cb->irq_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) err_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	iounmap(cb->crossbar_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) err_cb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	kfree(cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int __init irqcrossbar_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				   struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct irq_domain *parent_domain, *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		pr_err("%pOF: no parent, giving up\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	parent_domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (!parent_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		pr_err("%pOF: unable to obtain parent domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	err = crossbar_of_init(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	domain = irq_domain_add_hierarchy(parent_domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 					  cb->max_crossbar_sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					  node, &crossbar_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 					  NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		pr_err("%pOF: failed to allocated domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);