Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  CLPS711X IRQ driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLPS711X_INTSR1	(0x0240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLPS711X_INTMR1	(0x0280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLPS711X_BLEOI	(0x0600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLPS711X_MCEOI	(0x0640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLPS711X_TEOI	(0x0680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLPS711X_TC1EOI	(0x06c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLPS711X_TC2EOI	(0x0700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLPS711X_RTCEOI	(0x0740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLPS711X_UMSEOI	(0x0780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLPS711X_COEOI	(0x07c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLPS711X_INTSR2	(0x1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLPS711X_INTMR2	(0x1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLPS711X_SRXEOF	(0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLPS711X_KBDEOI	(0x1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLPS711X_INTSR3	(0x2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLPS711X_INTMR3	(0x2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLPS711X_FLAG_EN	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLPS711X_FLAG_FIQ	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	phys_addr_t	eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) } clps711x_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	[1]	= { CLPS711X_FLAG_FIQ, CLPS711X_BLEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	[3]	= { CLPS711X_FLAG_FIQ, CLPS711X_MCEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[4]	= { CLPS711X_FLAG_EN, CLPS711X_COEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	[5]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	[6]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[7]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[8]	= { CLPS711X_FLAG_EN, CLPS711X_TC1EOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[9]	= { CLPS711X_FLAG_EN, CLPS711X_TC2EOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[10]	= { CLPS711X_FLAG_EN, CLPS711X_RTCEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[11]	= { CLPS711X_FLAG_EN, CLPS711X_TEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[12]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[13]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[14]	= { CLPS711X_FLAG_EN, CLPS711X_UMSEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[15]	= { CLPS711X_FLAG_EN, CLPS711X_SRXEOF, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[16]	= { CLPS711X_FLAG_EN, CLPS711X_KBDEOI, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	[17]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	[18]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[28]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[29]	= { CLPS711X_FLAG_EN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[32]	= { CLPS711X_FLAG_FIQ, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	void __iomem		*intmr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	void __iomem		*intsr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct irq_domain_ops	ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) } *clps711x_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static asmlinkage void __exception_irq_entry clps711x_irqh(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		irqstat = readw_relaxed(clps711x_intc->intmr[0]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			  readw_relaxed(clps711x_intc->intsr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		if (irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			handle_domain_irq(clps711x_intc->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					  fls(irqstat) - 1, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		irqstat = readw_relaxed(clps711x_intc->intmr[1]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			  readw_relaxed(clps711x_intc->intsr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			handle_domain_irq(clps711x_intc->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					  fls(irqstat) - 1 + 16, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	} while (irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void clps711x_intc_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void clps711x_intc_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	void __iomem *intmr = clps711x_intc->intmr[hwirq / 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tmp = readl_relaxed(intmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tmp &= ~(1 << (hwirq % 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	writel_relaxed(tmp, intmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void clps711x_intc_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	void __iomem *intmr = clps711x_intc->intmr[hwirq / 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tmp = readl_relaxed(intmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tmp |= 1 << (hwirq % 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	writel_relaxed(tmp, intmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct irq_chip clps711x_intc_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.name		= "clps711x-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.irq_eoi	= clps711x_intc_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.irq_mask	= clps711x_intc_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.irq_unmask	= clps711x_intc_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int __init clps711x_intc_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	irq_flow_handler_t handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (!clps711x_irqs[hw].flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (clps711x_irqs[hw].flags & CLPS711X_FLAG_FIQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		flags |= IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} else if (clps711x_irqs[hw].eoi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		handler = handle_fasteoi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Clear down pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (clps711x_irqs[hw].eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	irq_set_chip_and_handler(virq, &clps711x_intc_chip, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	irq_modify_status(virq, IRQ_NOPROBE, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int __init _clps711x_intc_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				      phys_addr_t base, resource_size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	clps711x_intc = kzalloc(sizeof(*clps711x_intc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!clps711x_intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	clps711x_intc->base = ioremap(base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (!clps711x_intc->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	clps711x_intc->intsr[0] = clps711x_intc->base + CLPS711X_INTSR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	clps711x_intc->intmr[0] = clps711x_intc->base + CLPS711X_INTMR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clps711x_intc->intsr[1] = clps711x_intc->base + CLPS711X_INTSR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	clps711x_intc->intmr[1] = clps711x_intc->base + CLPS711X_INTMR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clps711x_intc->intsr[2] = clps711x_intc->base + CLPS711X_INTSR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	clps711x_intc->intmr[2] = clps711x_intc->base + CLPS711X_INTMR3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	writel_relaxed(0, clps711x_intc->intmr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	writel_relaxed(0, clps711x_intc->intmr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	writel_relaxed(0, clps711x_intc->intmr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	err = irq_alloc_descs(-1, 0, ARRAY_SIZE(clps711x_irqs), numa_node_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	clps711x_intc->ops.map = clps711x_intc_irq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	clps711x_intc->ops.xlate = irq_domain_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	clps711x_intc->domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		irq_domain_add_legacy(np, ARRAY_SIZE(clps711x_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				      0, 0, &clps711x_intc->ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (!clps711x_intc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		goto out_irqfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	irq_set_default_host(clps711x_intc->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	set_handle_irq(clps711x_irqh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #ifdef CONFIG_FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	init_FIQ(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) out_irqfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	irq_free_descs(0, ARRAY_SIZE(clps711x_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	iounmap(clps711x_intc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) out_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	kfree(clps711x_intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __init clps711x_intc_init(phys_addr_t base, resource_size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	BUG_ON(_clps711x_intc_init(NULL, base, size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_IRQCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int __init clps711x_intc_init_dt(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	err = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return _clps711x_intc_init(np, res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IRQCHIP_DECLARE(clps711x, "cirrus,ep7209-intc", clps711x_intc_init_dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif