^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct brcmstb_intc_init_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) irq_flow_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int cpu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int cpu_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int cpu_mask_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int cpu_mask_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int cpu_mask_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register offsets in the L2 latched interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct brcmstb_intc_init_params l2_edge_intc_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .handler = handle_edge_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .cpu_status = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .cpu_clear = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .cpu_mask_status = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .cpu_mask_set = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .cpu_mask_clear = 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Register offsets in the L2 level interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .handler = handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .cpu_status = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .cpu_clear = -1, /* Register not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .cpu_mask_status = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .cpu_mask_set = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .cpu_mask_clear = 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* L2 intc private data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct brcmstb_l2_intc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int status_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int mask_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool can_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 saved_mask; /* for suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @d: irq_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Chip has separate enable/disable registers instead of a single mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * register and pending interrupt is acknowledged by setting a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Note: This function is generic and could easily be added to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * generic irqchip implementation if there ever becomes a will to do so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * e.g.: https://patchwork.kernel.org/patch/9831047/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void brcmstb_l2_mask_and_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 mask = d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) irq_reg_writel(gc, mask, ct->regs.disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *ct->mask_cache &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) irq_reg_writel(gc, mask, ct->regs.ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) status = irq_reg_readl(b->gc, b->status_offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ~(irq_reg_readl(b->gc, b->mask_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) raw_spin_lock(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) handle_bad_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) raw_spin_unlock(&desc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) irq = ffs(status) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) status &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) generic_handle_irq(irq_linear_revmap(b->domain, irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } while (status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void brcmstb_l2_intc_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct brcmstb_l2_intc_data *b = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irq_gc_lock_irqsave(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Save the current mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (b->can_wake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Program the wakeup mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void brcmstb_l2_intc_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct brcmstb_l2_intc_data *b = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) irq_gc_lock_irqsave(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ct->chip.irq_ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Clear unmasked non-wakeup interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ct->regs.ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Restore the saved mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int __init brcmstb_l2_intc_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct brcmstb_intc_init_params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *init_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct brcmstb_l2_intc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_err("failed to remap intc L2 registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Disable all interrupts by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(0xffffffff, base + init_params->cpu_mask_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Wakeup interrupts may be retained from S5 (cold boot) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!data->can_wake && (init_params->cpu_clear >= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(0xffffffff, base + init_params->cpu_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) parent_irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_err("failed to find parent interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data->domain = irq_domain_add_linear(np, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!data->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* MIPS chips strapped for BE will automagically configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * peripheral registers for CPU-native byte order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) flags |= IRQ_GC_BE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Allocate a single Generic IRQ chip for this node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) np->full_name, init_params->handler, clr, 0, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pr_err("failed to allocate generic irq chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Set the IRQ chaining logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) brcmstb_l2_intc_irq_handle, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data->gc = irq_get_domain_generic_chip(data->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) data->gc->reg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data->gc->private = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) data->status_offset = init_params->cpu_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) data->mask_offset = init_params->cpu_mask_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ct = data->gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (init_params->cpu_clear >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ct->regs.ack = init_params->cpu_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ct->chip.irq_ack = irq_gc_ack_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* No Ack - but still slightly more efficient to define this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ct->chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ct->regs.disable = init_params->cpu_mask_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ct->regs.mask = init_params->cpu_mask_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ct->regs.enable = init_params->cpu_mask_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ct->chip.irq_resume = brcmstb_l2_intc_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (data->can_wake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* This IRQ chip can wake the system, set all child interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * in wake_enabled mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) data->gc->wake_enabled = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ct->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enable_irq_wake(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) irq_domain_remove(data->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) brcmstb_l2_edge_intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) brcmstb_l2_edge_intc_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) brcmstb_l2_lvl_intc_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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