^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom BCM7120 style Level 2 interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Register offset in the L2 interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IRQEN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IRQSTAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX_WORDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_MAPPINGS (MAX_WORDS * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IRQS_PER_WORD 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct bcm7120_l1_intc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct bcm7120_l2_intc_data *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 irq_map_mask[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct bcm7120_l2_intc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *map_base[MAX_MAPPINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *pair_base[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int en_offset[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int stat_offset[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool can_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 irq_fwd_mask[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct bcm7120_l1_intc_data *l1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int num_parent_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const __be32 *map_mask_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct bcm7120_l2_intc_data *b = data->b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) for (idx = 0; idx < b->n_words; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int base = idx * IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct irq_chip_generic *gc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) irq_get_domain_generic_chip(b->domain, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pending = irq_reg_readl(gc, b->stat_offset[idx]) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) gc->mask_cache &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) data->irq_map_mask[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) generic_handle_irq(irq_find_mapping(b->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) base + hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct bcm7120_l2_intc_data *b = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (b->can_wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct irq_chip_type *ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Restore the saved mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int bcm7120_l2_intc_init_one(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct bcm7120_l2_intc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int irq, u32 *valid_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) parent_irq = irq_of_parse_and_map(dn, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("failed to map interrupt %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* For multiple parent IRQs with multiple words, this looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * We need to associate a given parent interrupt with its corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * map_mask in order to mask the status register with it because we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * have the same handler being called for multiple parent interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * This is typically something needed on BCM7xxx (STB chips).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (idx = 0; idx < data->n_words; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (data->map_mask_prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) l1_data->irq_map_mask[idx] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) be32_to_cpup(data->map_mask_prop +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq * data->n_words + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) l1_data->irq_map_mask[idx] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) valid_mask[idx] |= l1_data->irq_map_mask[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) l1_data->b = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) irq_set_chained_handler_and_data(parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bcm7120_l2_intc_irq_handle, l1_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (data->can_wake)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enable_irq_wake(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct bcm7120_l2_intc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) data->map_base[0] = of_iomap(dn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!data->map_base[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pr_err("unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) data->pair_base[0] = data->map_base[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) data->en_offset[0] = IRQEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) data->stat_offset[0] = IRQSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) data->n_words = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) data->irq_fwd_mask, data->n_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret != 0 && ret != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* property exists but has the wrong number of words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_err("invalid brcm,int-fwd-mask property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!data->map_mask_prop ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pr_err("invalid brcm,int-map-mask property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct bcm7120_l2_intc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int gc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int map_idx = gc_idx * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *en = of_iomap(dn, map_idx + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *stat = of_iomap(dn, map_idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __iomem *base = min(en, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data->map_base[map_idx + 0] = en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) data->map_base[map_idx + 1] = stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) data->pair_base[gc_idx] = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data->en_offset[gc_idx] = en - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data->stat_offset[gc_idx] = stat - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!gc_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pr_err("unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) data->n_words = gc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int __init bcm7120_l2_intc_probe(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int (*iomap_regs_fn)(struct device_node *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct bcm7120_l2_intc_data *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const char *intc_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct bcm7120_l2_intc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int idx, irq, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 valid_mask[MAX_WORDS] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) data->num_parent_irqs = of_irq_count(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (data->num_parent_irqs <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pr_err("invalid number of parent interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!data->l1_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto out_free_l1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = iomap_regs_fn(dn, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto out_free_l1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (irq = 0; irq < data->num_parent_irqs; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto out_free_l1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) &irq_generic_chip_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!data->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out_free_l1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* MIPS chips strapped for BE will automagically configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * peripheral registers for CPU-native byte order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) flags = IRQ_GC_INIT_MASK_CACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) flags |= IRQ_GC_BE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dn->full_name, handle_level_irq, clr, 0, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_err("failed to allocate generic irq chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (idx = 0; idx < data->n_words; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) irq = idx * IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) gc = irq_get_domain_generic_chip(data->domain, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) gc->unused = 0xffffffff & ~valid_mask[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) gc->private = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) gc->reg_base = data->pair_base[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ct->regs.mask = data->en_offset[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* gc->reg_base is defined and so is gc->writel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) irq_reg_writel(gc, data->irq_fwd_mask[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) data->en_offset[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ct->chip.irq_mask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ct->chip.irq_unmask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ct->chip.irq_ack = irq_gc_noop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gc->suspend = bcm7120_l2_intc_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gc->resume = bcm7120_l2_intc_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Initialize mask-cache, in case we need it for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * saving/restoring fwd mask even w/o any child interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * installed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (data->can_wake) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* This IRQ chip can wake the system, set all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * relevant child interupts in wake_enabled mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gc->wake_enabled = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gc->wake_enabled &= ~gc->unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ct->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) intc_name, dn, data->num_parent_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq_domain_remove(data->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) out_free_l1_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) kfree(data->l1_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) for (idx = 0; idx < MAX_MAPPINGS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (data->map_base[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) iounmap(data->map_base[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "BCM7120 L2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "BCM3380 L2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bcm7120_l2_intc_probe_7120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) bcm7120_l2_intc_probe_3380);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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