Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Broadcom BCM7038 style Level 1 interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Kevin Cernekee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IRQS_PER_WORD		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX_WORDS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct bcm7038_l1_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct bcm7038_l1_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	raw_spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int		n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct bcm7038_l1_cpu	*cpus[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct list_head	list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32			wake_mask[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32			irq_fwd_mask[MAX_WORDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8			affinity[MAX_WORDS * IRQS_PER_WORD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct bcm7038_l1_cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	void __iomem		*map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32			mask_cache[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * 7038:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *   0x1000_1400: W0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *   0x1000_1404: W1_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *   0x1000_1408: W0_MASK_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *   0x1000_140c: W1_MASK_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *   0x1000_1410: W0_MASK_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *   0x1000_1414: W1_MASK_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *   0x1000_1418: W0_MASK_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *   0x1000_141c: W1_MASK_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * 7445:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *   0xf03e_1500: W0_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *   0xf03e_1504: W1_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *   0xf03e_1508: W2_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *   0xf03e_150c: W3_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *   0xf03e_1510: W4_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *   0xf03e_1514: W0_MASK_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *   0xf03e_1518: W1_MASK_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *   [...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				      unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return (0 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 					   unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return (1 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 					unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return (2 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 					unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return (3 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline u32 l1_readl(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return ioread32be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline void l1_writel(u32 val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		iowrite32be(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void bcm7038_l1_irq_handle(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct bcm7038_l1_cpu *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	cpu = intc->cpus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	for (idx = 0; idx < intc->n_words; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		int base = idx * IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		unsigned long pending, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			  ~cpu->mask_cache[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			generic_handle_irq(irq_find_mapping(intc->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 							    base + hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			reg_mask_clr(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	intc->cpus[cpu_idx]->mask_cache[word] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	l1_writel(mask, intc->cpus[cpu_idx]->map_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			reg_mask_set(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void bcm7038_l1_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void bcm7038_l1_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int bcm7038_l1_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				   const struct cpumask *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				   bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	irq_hw_number_t hw = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 word = hw / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 mask = BIT(hw % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	bool was_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			  mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	__bcm7038_l1_mask(d, intc->affinity[hw]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	intc->affinity[hw] = first_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!was_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		__bcm7038_l1_unmask(d, first_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void bcm7038_l1_cpu_offline(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct cpumask *mask = irq_data_get_affinity_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	cpumask_t new_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* This CPU was not on the affinity mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!cpumask_test_cpu(cpu, mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (cpumask_weight(mask) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 * Multiple CPU affinity, remove this CPU from the affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		 * mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		cpumask_copy(&new_affinity, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		cpumask_clear_cpu(cpu, &new_affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		/* Only CPU, put on the lowest online CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		cpumask_clear(&new_affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	irq_set_affinity_locked(d, &new_affinity, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int __init bcm7038_l1_init_one(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				      unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				      struct bcm7038_l1_chip *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	resource_size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct bcm7038_l1_cpu *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	unsigned int i, n_words, parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (of_address_to_resource(dn, idx, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	sz = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	n_words = sz / REG_BYTES_PER_IRQ_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (n_words > MAX_WORDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	else if (!intc->n_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		intc->n_words = n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	else if (intc->n_words != n_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 					 intc->irq_fwd_mask, n_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret != 0 && ret != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		/* property exists but has the wrong number of words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		pr_err("invalid brcm,int-fwd-mask property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	cpu->map_base = ioremap(res.start, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (!cpu->map_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	for (i = 0; i < n_words; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		l1_writel(~intc->irq_fwd_mask[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			  cpu->map_base + reg_mask_set(intc, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		l1_writel(intc->irq_fwd_mask[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			  cpu->map_base + reg_mask_clr(intc, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	parent_irq = irq_of_parse_and_map(dn, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		pr_err("failed to map parent interrupt %d\n", parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		enable_irq_wake(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					 intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * used because the struct chip_type suspend/resume hooks are not called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * unless chip_type is hooked onto a generic_chip. Since this driver does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  * not use generic_chip, we need to manually hook our resume/suspend to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * syscore_ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static LIST_HEAD(bcm7038_l1_intcs_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int bcm7038_l1_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct bcm7038_l1_chip *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int boot_cpu, word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* Wakeup interrupt should only come from the boot cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	boot_cpu = cpu_logical_map(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	boot_cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		for (word = 0; word < intc->n_words; word++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			val = intc->wake_mask[word] | intc->irq_fwd_mask[word];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			l1_writel(~val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			l1_writel(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void bcm7038_l1_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct bcm7038_l1_chip *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	int boot_cpu, word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	boot_cpu = cpu_logical_map(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	boot_cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		for (word = 0; word < intc->n_words; word++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct syscore_ops bcm7038_l1_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.suspend	= bcm7038_l1_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.resume		= bcm7038_l1_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		intc->wake_mask[word] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		intc->wake_mask[word] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct irq_chip bcm7038_l1_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.name			= "bcm7038-l1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.irq_mask		= bcm7038_l1_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.irq_unmask		= bcm7038_l1_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.irq_set_affinity	= bcm7038_l1_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.irq_cpu_offline	= bcm7038_l1_cpu_offline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.irq_set_wake		= bcm7038_l1_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			  irq_hw_number_t hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct bcm7038_l1_chip *intc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	u32 mask = BIT(hw_irq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	u32 word = hw_irq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (intc->irq_fwd_mask[word] & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	irq_set_chip_data(virq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct irq_domain_ops bcm7038_l1_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.xlate			= irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	.map			= bcm7038_l1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int __init bcm7038_l1_of_init(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct bcm7038_l1_chip *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (!intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	raw_spin_lock_init(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	for_each_possible_cpu(idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		ret = bcm7038_l1_init_one(dn, idx, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			if (idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			pr_err("failed to remap intc L1 registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 					     &bcm7038_l1_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 					     intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	if (!intc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	/* Add bcm7038_l1_chip into a list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	raw_spin_lock(&bcm7038_l1_intcs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	raw_spin_unlock(&bcm7038_l1_intcs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	if (list_is_singular(&bcm7038_l1_intcs_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		register_syscore_ops(&bcm7038_l1_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		dn, IRQS_PER_WORD * intc->n_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	for_each_possible_cpu(idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		if (cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 			if (cpu->map_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 				iounmap(cpu->map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 			kfree(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	kfree(intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);