Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Broadcom BCM6345 style Level 1 interrupt controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2015 Simon Arlott
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This is based on the BCM7038 (which supports SMP) but with a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * enable register instead of separate mask/set/clear registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The BCM3380 has a similar mask/status register layout, but each pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * of words is at separate locations (and SMP is not supported).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * ENABLE/STATUS words are packed next to each other for each CPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * BCM6368:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   0x1000_0020: CPU0_W0_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *   0x1000_0024: CPU0_W1_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *   0x1000_0028: CPU0_W0_STATUS		IRQs 31-63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *   0x1000_002c: CPU0_W1_STATUS		IRQs 0-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *   0x1000_0030: CPU1_W0_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *   0x1000_0034: CPU1_W1_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *   0x1000_0038: CPU1_W0_STATUS		IRQs 31-63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *   0x1000_003c: CPU1_W1_STATUS		IRQs 0-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * BCM63168:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *   0x1000_0020: CPU0_W0_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *   0x1000_0024: CPU0_W1_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *   0x1000_0028: CPU0_W2_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *   0x1000_002c: CPU0_W3_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *   0x1000_0030: CPU0_W0_STATUS	IRQs 96-127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *   0x1000_0034: CPU0_W1_STATUS	IRQs 64-95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *   0x1000_0038: CPU0_W2_STATUS	IRQs 32-63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *   0x1000_003c: CPU0_W3_STATUS	IRQs 0-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *   0x1000_0040: CPU1_W0_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *   0x1000_0044: CPU1_W1_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *   0x1000_0048: CPU1_W2_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *   0x1000_004c: CPU1_W3_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *   0x1000_0050: CPU1_W0_STATUS	IRQs 96-127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *   0x1000_0054: CPU1_W1_STATUS	IRQs 64-95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *   0x1000_0058: CPU1_W2_STATUS	IRQs 32-63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *   0x1000_005c: CPU1_W3_STATUS	IRQs 0-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * IRQs are numbered in CPU native endian order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * (which is big-endian in these examples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IRQS_PER_WORD		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define REG_BYTES_PER_IRQ_WORD	(sizeof(u32) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct bcm6345_l1_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct bcm6345_l1_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	raw_spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	unsigned int		n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct irq_domain	*domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct cpumask		cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct bcm6345_l1_cpu	*cpus[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct bcm6345_l1_cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	void __iomem		*map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned int		parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32			enable_cache[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 					   unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return (1 * intc->n_words - word - 1) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return (0 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				      unsigned int word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return (2 * intc->n_words - word - 1) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return (1 * intc->n_words + word) * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 					struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void bcm6345_l1_irq_handle(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct bcm6345_l1_cpu *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	cpu = intc->cpus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	for (idx = 0; idx < intc->n_words; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		int base = idx * IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			irq = irq_linear_revmap(intc->domain, base + hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				spurious_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline void __bcm6345_l1_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned int cpu_idx = cpu_for_irq(intc, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	intc->cpus[cpu_idx]->enable_cache[word] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void __bcm6345_l1_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int cpu_idx = cpu_for_irq(intc, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void bcm6345_l1_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	__bcm6345_l1_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void bcm6345_l1_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	__bcm6345_l1_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int bcm6345_l1_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				   const struct cpumask *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				   bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 word = d->hwirq / IRQS_PER_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	unsigned int old_cpu = cpu_for_irq(intc, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned int new_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct cpumask valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (!cpumask_and(&valid, &intc->cpumask, dest))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	new_cpu = cpumask_any_and(&valid, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (new_cpu >= nr_cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	dest = cpumask_of(new_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	raw_spin_lock_irqsave(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (old_cpu != new_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			__bcm6345_l1_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		cpumask_copy(irq_data_get_affinity_mask(d), dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			__bcm6345_l1_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		cpumask_copy(irq_data_get_affinity_mask(d), dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	raw_spin_unlock_irqrestore(&intc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return IRQ_SET_MASK_OK_NOCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int __init bcm6345_l1_init_one(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				      unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				      struct bcm6345_l1_chip *intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	resource_size_t sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct bcm6345_l1_cpu *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned int i, n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (of_address_to_resource(dn, idx, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	sz = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	n_words = sz / REG_BYTES_PER_IRQ_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!intc->n_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		intc->n_words = n_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	else if (intc->n_words != n_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	cpu->map_base = ioremap(res.start, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (!cpu->map_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	for (i = 0; i < n_words; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		cpu->enable_cache[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		__raw_writel(0, cpu->map_base + reg_enable(intc, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	cpu->parent_irq = irq_of_parse_and_map(dn, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!cpu->parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	irq_set_chained_handler_and_data(cpu->parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 						bcm6345_l1_irq_handle, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct irq_chip bcm6345_l1_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.name			= "bcm6345-l1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.irq_mask		= bcm6345_l1_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.irq_unmask		= bcm6345_l1_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.irq_set_affinity	= bcm6345_l1_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			  irq_hw_number_t hw_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	irq_set_chip_and_handler(virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		&bcm6345_l1_irq_chip, handle_percpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	irq_set_chip_data(virq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct irq_domain_ops bcm6345_l1_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.xlate			= irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.map			= bcm6345_l1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int __init bcm6345_l1_of_init(struct device_node *dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct bcm6345_l1_chip *intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	intc = kzalloc(sizeof(*intc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (!intc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	for_each_possible_cpu(idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		ret = bcm6345_l1_init_one(dn, idx, intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			pr_err("failed to init intc L1 for cpu %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				idx, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			cpumask_set_cpu(idx, &intc->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!cpumask_weight(&intc->cpumask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	raw_spin_lock_init(&intc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 					     &bcm6345_l1_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					     intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!intc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			IRQS_PER_WORD * intc->n_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	for_each_cpu(idx, &intc->cpumask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		pr_info("  CPU%u at MMIO 0x%p (irq = %d)\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				cpu->map_base, cpu->parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	for_each_possible_cpu(idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		if (cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			if (cpu->map_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				iounmap(cpu->map_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			kfree(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	kfree(intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);