Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2015 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irqchip/irq-bcm2836.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct bcm2836_arm_irqchip_intc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct bcm2836_arm_irqchip_intc intc  __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 						 unsigned int bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 						 int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	void __iomem *reg = intc.base + reg_offset + 4 * cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	writel(readl(reg) & ~BIT(bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 						   unsigned int bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 						 int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem *reg = intc.base + reg_offset + 4 * cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	writel(readl(reg) | BIT(bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					     d->hwirq - LOCAL_IRQ_CNTPSIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					     smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					       d->hwirq - LOCAL_IRQ_CNTPSIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 					       smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static struct irq_chip bcm2836_arm_irqchip_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.name		= "bcm2836-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.irq_mask	= bcm2836_arm_irqchip_mask_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.irq_unmask	= bcm2836_arm_irqchip_unmask_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct irq_chip bcm2836_arm_irqchip_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.name		= "bcm2836-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.irq_mask	= bcm2836_arm_irqchip_mask_pmu_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.irq_unmask	= bcm2836_arm_irqchip_unmask_pmu_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct irq_chip bcm2836_arm_irqchip_gpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.name		= "bcm2836-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.irq_mask	= bcm2836_arm_irqchip_mask_gpu_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.irq_unmask	= bcm2836_arm_irqchip_unmask_gpu_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static struct irq_chip bcm2836_arm_irqchip_dummy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.name		= "bcm2836-dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.irq_eoi	= bcm2836_arm_irqchip_dummy_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int bcm2836_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	switch (hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case LOCAL_IRQ_MAILBOX0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		chip = &bcm2836_arm_irqchip_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case LOCAL_IRQ_CNTPSIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case LOCAL_IRQ_CNTPNSIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	case LOCAL_IRQ_CNTHPIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case LOCAL_IRQ_CNTVIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		chip = &bcm2836_arm_irqchip_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case LOCAL_IRQ_GPU_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		chip = &bcm2836_arm_irqchip_gpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case LOCAL_IRQ_PMU_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		chip = &bcm2836_arm_irqchip_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pr_warn_once("Unexpected hw irq: %lu\n", hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	irq_set_percpu_devid(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	irq_domain_set_info(d, irq, hw, chip, d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			    handle_percpu_devid_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	irq_set_status_flags(irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		u32 hwirq = ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		handle_domain_irq(intc.domain, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct irq_domain *ipi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 mbox_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (mbox_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		int hwirq = ffs(mbox_val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		generic_handle_irq(irq_find_mapping(ipi_domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void bcm2836_arm_irqchip_ipi_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	writel_relaxed(BIT(d->hwirq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		       intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					      const struct cpumask *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * Ensure that stores to normal memory are visible to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * other CPUs before issuing the IPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for_each_cpu(cpu, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct irq_chip bcm2836_arm_irqchip_ipi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.name		= "IPI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.irq_mask	= bcm2836_arm_irqchip_dummy_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.irq_unmask	= bcm2836_arm_irqchip_dummy_op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.irq_eoi	= bcm2836_arm_irqchip_ipi_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.ipi_send_mask	= bcm2836_arm_irqchip_ipi_send_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 					 unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					 unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		irq_set_percpu_devid(virq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				    d->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 				    handle_percpu_devid_fasteoi_ipi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				    NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					 unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					 unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Not freeing IPIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct irq_domain_ops ipi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.alloc	= bcm2836_arm_irqchip_ipi_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.free	= bcm2836_arm_irqchip_ipi_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int bcm2836_cpu_starting(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					       cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int bcm2836_cpu_dying(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					     cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BITS_PER_MBOX	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void __init bcm2836_arm_irqchip_smp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct irq_fwspec ipi_fwspec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.fwnode		= intc.domain->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.param_count	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.param		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			[0]	= LOCAL_IRQ_MAILBOX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int base_ipi, mux_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (WARN_ON(mux_irq <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 					      BITS_PER_MBOX, &ipi_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 					      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (WARN_ON(!ipi_domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					   NUMA_NO_NODE, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 					   false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (WARN_ON(!base_ipi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	irq_set_chained_handler_and_data(mux_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					 bcm2836_arm_irqchip_handle_ipi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* Unmask IPIs to the boot CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			  "irqchip/bcm2836:starting", bcm2836_cpu_starting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			  bcm2836_cpu_dying);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define bcm2836_arm_irqchip_smp_init()	do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.map = bcm2836_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * The LOCAL_IRQ_CNT* timer firings are based off of the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * oscillator with some scaling.  The firmware sets up CNTFRQ to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * report 19.2Mhz, but doesn't set up the scaling registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void bcm2835_init_local_timer_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * Set the timer to source from the 19.2Mhz crystal clock (bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * 8 unset), and only increment by 1 instead of 2 (bit 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 * unset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	writel(0, intc.base + LOCAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * Set the timer prescaler to 1:1 (timer freq = input freq *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * 2**31 / prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	writel(0x80000000, intc.base + LOCAL_PRESCALER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 						      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	intc.base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!intc.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		panic("%pOF: unable to map local interrupt registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	bcm2835_init_local_timer_frequency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 					    &bcm2836_arm_irqchip_intc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 					    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (!intc.domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		panic("%pOF: unable to create IRQ domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	bcm2836_arm_irqchip_smp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	set_handle_irq(bcm2836_arm_irqchip_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		bcm2836_arm_irqchip_l1_intc_of_init);