Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2010 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * to look in the bank 1 status register for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * status register, but bank 0 bit 8 is _not_ set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Quirk 2: You can't mask the register 1/2 pending interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * In a proper cascaded interrupt controller, the interrupt lines with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * cascaded interrupt controllers on them are just normal interrupt lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * You can mask the interrupts and get on with things. With this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * you can't do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Those interrupts that have shortcuts can only be masked/unmasked in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * their respective banks' enable/disable registers. Doing so in the bank 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * enable/disable registers has no effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * The FIQ control register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *  Bit    7: Enable FIQ generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *  Bits  8+: Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * An interrupt must be disabled before configuring it for FIQ generation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * otherwise both handlers will fire at the same time!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Put the bank and irq (32 bits) into the hwirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAKE_HWIRQ(b, n)	((b << 5) | (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HWIRQ_BANK(i)		(i >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HWIRQ_BIT(i)		BIT(i & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define NR_IRQS_BANK0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BANK0_HWIRQ_MASK	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Shortcuts can't be disabled so any unknown new ones need to be masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SHORTCUT1_MASK		0x00007c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SHORTCUT2_MASK		0x001f8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SHORTCUT_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BANK1_HWIRQ		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BANK2_HWIRQ		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BANK0_VALID_MASK	(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 					| SHORTCUT1_MASK | SHORTCUT2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_FIQ_CONTROL		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define FIQ_CONTROL_ENABLE	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define NR_BANKS		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define IRQS_PER_BANK		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const int bank_irqs[] __initconst = { 8, 32, 32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const int shortcuts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	7, 9, 10, 18, 19,		/* Bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	21, 22, 23, 24, 25, 30		/* Bank 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct armctrl_ic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	void __iomem *pending[NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	void __iomem *enable[NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem *disable[NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct armctrl_ic intc __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void __exception_irq_entry bcm2835_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void bcm2836_chained_handle_irq(struct irq_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void armctrl_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void armctrl_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct irq_chip armctrl_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.name = "ARMCTRL-level",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.irq_mask = armctrl_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.irq_unmask = armctrl_unmask_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long *out_hwirq, unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (WARN_ON(intsize != 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (WARN_ON(intspec[0] >= NR_BANKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	*out_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct irq_domain_ops armctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.xlate = armctrl_xlate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int __init armctrl_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				  struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				  bool is_2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int irq, b, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		panic("%pOF: unable to map IC registers\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			&armctrl_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!intc.domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		panic("%pOF: unable to create IRQ domain\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	for (b = 0; b < NR_BANKS; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		intc.pending[b] = base + reg_pending[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		intc.enable[b] = base + reg_enable[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		intc.disable[b] = base + reg_disable[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		for (i = 0; i < bank_irqs[b]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			BUG_ON(irq <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			irq_set_chip_and_handler(irq, &armctrl_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		reg = readl_relaxed(intc.enable[b]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			writel_relaxed(reg, intc.disable[b]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			pr_err(FW_BUG "Bootloader left irq enabled: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			       "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	reg = readl_relaxed(base + REG_FIQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (reg & FIQ_CONTROL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		writel_relaxed(0, base + REG_FIQ_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pr_err(FW_BUG "Bootloader left fiq enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (is_2836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		int parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			panic("%pOF: unable to get parent interrupt.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			      node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		set_handle_irq(bcm2835_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int __init bcm2835_armctrl_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					  struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return armctrl_of_init(node, parent, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int __init bcm2836_armctrl_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 					  struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return armctrl_of_init(node, parent, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Handle each interrupt across the entire interrupt controller.  This reads the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * status register before handling each interrupt, which is necessary given that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static u32 armctrl_translate_bank(int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 stat = readl_relaxed(intc.pending[bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return MAKE_HWIRQ(bank, ffs(stat) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static u32 armctrl_translate_shortcut(int bank, u32 stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u32 get_next_armctrl_hwirq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (stat == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	else if (stat & BANK0_HWIRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	else if (stat & SHORTCUT1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	else if (stat & SHORTCUT2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	else if (stat & BANK1_HWIRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return armctrl_translate_bank(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	else if (stat & BANK2_HWIRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return armctrl_translate_bank(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void __exception_irq_entry bcm2835_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		handle_domain_irq(intc.domain, hwirq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void bcm2836_chained_handle_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		bcm2835_armctrl_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		bcm2836_armctrl_of_init);